Achievable frequency (fmax) is a widely used input con-straint for designs targeting Field-Programmable Gate Ar-rays (FPGA), because of its impact on design latency and throughput. fmax is limited by critical path delay, which is highly in uenced by lower-level details of the circuit imple-mentation such as technology mapping, placement and rout-ing. However, for high-level synthesis (HLS) design ows, it is challenging to evaluate the real critical delay at the behavioral level. Current HLS flows typically use module pre-characterization for delay estimates. However, we will demonstrate that such delay estimates are not sufficient to obtain high fmax and also minimize total execution latency. In this paper, we introduce a new HLS flow that inte-grates with Altera's Quartus synthesis and fast placement and routing (PAR) tool to obtain realistic post-PAR delay estimates. This integration enables an iterative flow that im-proves the performance of the design with both behavioral-level and circuit-level optimizations using realistic delay in-formation. We demonstrate our HLS flow produces up to 24% (on average 20%) improvement in fmax and upto 22% (on average 20%) improvement in execution latency. Fur-thermore, results demonstrate that our flow is able to achieve from 65% to 91% of the theoretical fmax on Stratix IV de-vices (550MHz).