Fast and accurate gate-level transient fault-simulation environment

Hungse Cha, Elizabeth M. Rudnick, Gwan S. Choi, Janak H. Patel, Ravishankar K. Iyer

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Mixed analog and digital mode simulators have been available for accurate transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. In this paper, we describe a gate-level transient fault simulation environment which has been developed based on realistic fault models. The simulation environment uses a timing fault simulator as well as a zero-delay parallel fault simulator. The timing fault simulator uses high level models of the actual transient fault phenomenon and latch operation to accurately propagate the fault effects to the latch outputs, after which point the zero-delay parallel fault simulator is used to speed up the simulation without any loss in accuracy. The simulation environment is demonstrated on ISCAS-89 sequential benchmark circuits.

Original languageEnglish (US)
Title of host publicationDigest of Papers - International Symposium on Fault-Tolerant Computing
Editors Anon
PublisherPubl by IEEE
Pages310-319
Number of pages10
ISBN (Print)0818636823
StatePublished - Dec 1 1993
EventProceedings of the 23rd International Symposium on Fault-Tolerant Computing - Toulouse, Fr
Duration: Jun 22 1993Jun 24 1993

Publication series

NameDigest of Papers - International Symposium on Fault-Tolerant Computing
ISSN (Print)0731-3071

Other

OtherProceedings of the 23rd International Symposium on Fault-Tolerant Computing
CityToulouse, Fr
Period6/22/936/24/93

ASJC Scopus subject areas

  • Hardware and Architecture

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