TY - GEN
T1 - Fast and accurate gate-level transient fault-simulation environment
AU - Cha, Hungse
AU - Rudnick, Elizabeth M.
AU - Choi, Gwan S.
AU - Patel, Janak H.
AU - Iyer, Ravishankar K.
PY - 1993
Y1 - 1993
N2 - Mixed analog and digital mode simulators have been available for accurate transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. In this paper, we describe a gate-level transient fault simulation environment which has been developed based on realistic fault models. The simulation environment uses a timing fault simulator as well as a zero-delay parallel fault simulator. The timing fault simulator uses high level models of the actual transient fault phenomenon and latch operation to accurately propagate the fault effects to the latch outputs, after which point the zero-delay parallel fault simulator is used to speed up the simulation without any loss in accuracy. The simulation environment is demonstrated on ISCAS-89 sequential benchmark circuits.
AB - Mixed analog and digital mode simulators have been available for accurate transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. In this paper, we describe a gate-level transient fault simulation environment which has been developed based on realistic fault models. The simulation environment uses a timing fault simulator as well as a zero-delay parallel fault simulator. The timing fault simulator uses high level models of the actual transient fault phenomenon and latch operation to accurately propagate the fault effects to the latch outputs, after which point the zero-delay parallel fault simulator is used to speed up the simulation without any loss in accuracy. The simulation environment is demonstrated on ISCAS-89 sequential benchmark circuits.
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M3 - Conference contribution
AN - SCOPUS:0027829860
SN - 0818636823
T3 - Digest of Papers - International Symposium on Fault-Tolerant Computing
SP - 310
EP - 319
BT - Digest of Papers - International Symposium on Fault-Tolerant Computing
A2 - Anon, null
PB - Publ by IEEE
T2 - Proceedings of the 23rd International Symposium on Fault-Tolerant Computing
Y2 - 22 June 1993 through 24 June 1993
ER -