Fabrication issues for multiple layers of SOI MOSFET devices

J. Yang, J. Denton, G. W. Neudeck, R. Bashir

Research output: Contribution to journalConference articlepeer-review


Two basic concerns for the fabrication of Multiple Layers of SOI (MLSOI) devices, namely, thermal budget and SOI island thickness are discussed in this paper. To electrically characterize the dopant lateral diffusion in thin SOI films, a lateral N+N N+ test structure was designed and simulated using TSUPREM-4 and MEDICI to investigate and measure the lateral diffusion in the SOI films. Simulation shows that the dopant profile in the thin SOI film is nice straight and perpendicular to the silicon and SiO2 interface. The SOI film thickness of small sized islands can be determined by employing a simple Transmission Line Model (TLM) structure.

Original languageEnglish (US)
Pages (from-to)79-82
Number of pages4
JournalBiennial University/Government/Industry Microelectronics Symposium - Proceedings
StatePublished - 1999
Externally publishedYes
EventProceedings of the 1999 13th Biennial University / Goverment / Industry Microelectronics Symposium (UGIM) - Minneapolis, MN, USA
Duration: Jun 20 1999Jun 23 1999

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of 'Fabrication issues for multiple layers of SOI MOSFET devices'. Together they form a unique fingerprint.

Cite this