Exploring multiplier architecture and layout for low power

Pascal C.H. Meier, Rob A. Rutenbar, L. Richard Carley

Research output: Contribution to journalConference articlepeer-review

Abstract

Multiplication represents a fundamental building block in all DSP tasks. Due to the large latency inherent in multiplication, schemes have been devised to minimize the delay. Two methods are common in current implementations: regular arrays and Wallace trees. Previous gate-level analyses have suggested that not only are Wallace trees faster than array schemes, they also consume much less power. However these analyses did not take wiring into account, resulting in optimistic timing and power estimates. We develop a simplified comparative layout methodology to analyze the effect of physical layout on these designs. Results for short bit-width (8, 16, 24 bit) DSP multipliers show that while wiring has a major impact on signal delay and power, Wallace trees still show roughly a 10% power advantage over array-based designs.

Original languageEnglish (US)
Pages (from-to)513-516
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
StatePublished - Jan 1 1996
EventProceedings of the 1996 IEEE Custom Integrated Circuits Conference - San Diego, CA, USA
Duration: May 5 1996May 8 1996

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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