Exploiting timing error resilience in processor architecture

John Sartori, Rakesh Kumar

Research output: Contribution to journalArticlepeer-review


Escalating variations in modern CMOS designs have become a threat to Moore's law. In light of the increasing costs of standard worst-case design practices, timing speculation has become a popular approach for dealing with static and dynamic non-determinism and increasing yield. Timing speculative architectures allow conservative guardbands to be relaxed, increasing efficiency at the expense of occasional errors, which are corrected or tolerated by an error resilience mechanism. Previous work has proposed circuit- or designlevel optimizations that manipulate the error rate behavior of a design to increase the efficiency of timing speculation. In this article, we investigate whether architectural optimizations can also manipulate error rate behavior to significantly increase the effectiveness of timing speculation. To this end, we demonstrate how error rate behavior indeed depends on processor architecture and that architectural optimizations can be used to manipulate the error rate behavior of a processor. Using timing speculation-aware architectural optimizations, we demonstrate enhanced overscaling and up to 29% additional energy savings for processors that employ Razor-based timing speculation.

Original languageEnglish (US)
Article number89
JournalTransactions on Embedded Computing Systems
Issue number2 SUPPL.
StatePublished - May 1 2013


  • Computer architecture
  • Energy efficiency
  • Error resilience
  • Timing speculation

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture


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