EXPLOITING PARALLEL MICROPROCESSOR MICROARCHITECTURES WITH A COMPILER CODE GENERATOR.

Wen mei W. Hwu, Pohua P. Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Several experiments using a versatile optimizing compiler to evaluate the benefit of four forms of microarchitectural parallelisms (multiple microoperations issued per cycle, multiple result-distribution buses, multiple execution units, and pipelined execution units) are described. The first 14 Livermore loops and 10 of the linpack subroutines are used as the preliminary benchmarks. The compiler generates optimized code for different microarchitecture configurations. It is shown how the compiler can help to derive a balanced design for high performance. For each given set of technology constraints, these experiments can be used to derive a cost-effective microarchitecture to execute each given set of workload programs at high speed.

Original languageEnglish (US)
Title of host publicationUnknown Host Publication Title
PublisherIEEE
Pages45-53
Number of pages9
ISBN (Print)0818608617
StatePublished - Jan 1 1988

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Microprocessor chips
Subroutines
Experiments
Costs

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Hwu, W. M. W., & Chang, P. P. (1988). EXPLOITING PARALLEL MICROPROCESSOR MICROARCHITECTURES WITH A COMPILER CODE GENERATOR. In Unknown Host Publication Title (pp. 45-53). IEEE.

EXPLOITING PARALLEL MICROPROCESSOR MICROARCHITECTURES WITH A COMPILER CODE GENERATOR. / Hwu, Wen mei W.; Chang, Pohua P.

Unknown Host Publication Title. IEEE, 1988. p. 45-53.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hwu, WMW & Chang, PP 1988, EXPLOITING PARALLEL MICROPROCESSOR MICROARCHITECTURES WITH A COMPILER CODE GENERATOR. in Unknown Host Publication Title. IEEE, pp. 45-53.
Hwu WMW, Chang PP. EXPLOITING PARALLEL MICROPROCESSOR MICROARCHITECTURES WITH A COMPILER CODE GENERATOR. In Unknown Host Publication Title. IEEE. 1988. p. 45-53
Hwu, Wen mei W. ; Chang, Pohua P. / EXPLOITING PARALLEL MICROPROCESSOR MICROARCHITECTURES WITH A COMPILER CODE GENERATOR. Unknown Host Publication Title. IEEE, 1988. pp. 45-53
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