Exploiting OS-Level Memory Offlining for DRAM Power Management

Seunghak Lee, Nam Sung Kim, Daehoon Kim

Research output: Contribution to journalArticlepeer-review


Power and energy consumed by main memory systems in data-center servers have increased as the DRAM capacity and bandwidth increase. Particularly, background power accounts for a considerable fraction of the total DRAM power consumption; the fraction will increase further in the near future, especially when slowing-down technology scaling forces us to provide necessary DRAM capacity through plugging in more DRAM modules or stacking more DRAM chips in a DRAM package. Although current DRAM architecture supports low power states at rank granularity that turn off some components during idle periods, techniques to exploit memory-level parallelism make the rank-granularity power state become ineffective. Furthermore, the long wake-up latency is one of obstacles to adopting aggressive power management (PM) with deep power-down states. By tackling the limitations, we propose OffDIMM that is a software-assisted DRAM PM collaborating with the OS-level memory onlining/offlining. OffDIMM maps a memory block in the address space of the OS to a subarray group or groups of DRAM, and sets a deep power-down state for the subarray group when offlining the block. Through the dynamic OS-level memory onlining/offlining based on the current memory usage, our experimental results show OffDIMM reduces background power by 24 percent on average without notable performance overheads.

Original languageEnglish (US)
Article number8846095
Pages (from-to)141-144
Number of pages4
JournalIEEE Computer Architecture Letters
Issue number2
StatePublished - Jul 1 2019


  • DRAM
  • memory offlining
  • power management

ASJC Scopus subject areas

  • Hardware and Architecture


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