EXPLOITING HORIZONTAL AND VERTICAL CONCURRENCY VIA THE HPSM MICROPROCESSOR.

Wen met W. Hwu, Yale N. Patt

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

HPSm is a single-chip microarchitecture that uses both vertical and horizontal concurrency. Experiments have been conducted to demonstrate the effectiveness of HPSm as compared to the Berkeley RISC II chip, which is similar to that of the SPUR chip. Evaluations have been done with both control-intensive and floating-point-intensive benchmarks. For both types of benchmarks, the authors show that the HPSm microarchitecture achieves significant speedup over the RISC/SPUR microarchitecture implemented with the same fabrication technology.

Original languageEnglish (US)
Title of host publicationMICRO
Subtitle of host publicationAnnual Microprogramming Workshop
PublisherACM
Pages154-161
Number of pages8
ISBN (Print)0897912500
StatePublished - Dec 1 1987

Publication series

NameMICRO: Annual Microprogramming Workshop
ISSN (Print)0361-2163

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Hwu, W. M. W., & Patt, Y. N. (1987). EXPLOITING HORIZONTAL AND VERTICAL CONCURRENCY VIA THE HPSM MICROPROCESSOR. In MICRO: Annual Microprogramming Workshop (pp. 154-161). (MICRO: Annual Microprogramming Workshop). ACM.