HPSm is a single-chip microarchitecture that uses both vertical and horizontal concurrency. Experiments have been conducted to demonstrate the effectiveness of HPSm as compared to the Berkeley RISC II chip, which is similar to that of the SPUR chip. Evaluations have been done with both control-intensive and floating-point-intensive benchmarks. For both types of benchmarks, the authors show that the HPSm microarchitecture achieves significant speedup over the RISC/SPUR microarchitecture implemented with the same fabrication technology.