Exploiting hierarchy in parallel computer networks to optimize collective operation performance

Nicholas T. Karonis, Bronis R. de Supinski, Ian Foster, William D Gropp, Ewing Lusk, John Bresnahan

Research output: Contribution to journalArticlepeer-review


The efficient implementation of collective communication operations has received much attention. Initial efforts modeled network communication and produced `optimal' trees based on those models. However, the models used by these initial efforts assumed equal point-to-point latencies between any two processes. This assumption is violated in heterogeneous systems such as clusters of SMPs and wide-area `computational grids', and as a result, collective operations that utilize the trees generated by these models perform suboptimally. In response, more recent work has focused on creating topology-aware trees for collective operations that minimize communication across slower channels (e.g., a wide-area network). While these efforts have significant communication benefits, they all limit their view of the network to only two layers. We present a strategy based upon a multilayer view of the network. By creating multilevel topology trees we take advantage of communication cost differences at every level in the network. We used this strategy to implement topology-aware versions of several MPI collective operations in MPICH-G, the Globus-enabled version of the popular MPICH implementation of the MPI standard. Using information about topology discovered by Globus, we construct these topology-aware trees automatically during execution, thus freeing the MPI application programmer from having to write special files or functions to describe the topology to the MPICH library. We present results demonstrating the advantages of our multilevel approach by comparing it to the default (topology-unaware) implementation provided by MPICH and a topology-aware two-layer implementation.

Original languageEnglish (US)
Pages (from-to)377-384
Number of pages8
JournalProceedings of the International Parallel Processing Symposium, IPPS
StatePublished - 2000

ASJC Scopus subject areas

  • Hardware and Architecture


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