EXPERIMENTS WITH HPS, A RESTRICTED DATA FLOW MICROARCHITECTURE FOR HIGH PERFORMANCE COMPUTERS.

Yale Patt; Wen mei Hwu; Stephen Melvin; Michael Shebanow; Chien Chen; Jiajuin Wei

EXPERIMENTS WITH HPS, A RESTRICTED DATA FLOW MICROARCHITECTURE FOR HIGH PERFORMANCE COMPUTERS.

Yale Patt, Wen mei Hwu, Stephen Melvin, Michael Shebanow, Chien Chen, Jiajuin Wei

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The authors have identified a new model of execution, restricted data flow, which is believed to have great potential for implementing a very-high-performance computing engine. This microengine is called HPS (High Performance Substrate) to reflect the notion that this model should be useful for implementing very dissimilar ISA architectures. Two extreme variations of HPS are specified, a minimal functionality version which can be implemented on a single chip, and a 'full throttle' version which has been proposed as a high performance implementation of the microvax-2 subset of the VAX architecture. Both models have been simulated, and measurements have been taken on several benchmarks. The results of some of these measurements are reported and compared with alternative styles of execution.

Original language	English (US)
Title of host publication	Proceedings - IEEE Computer Society International Conference
Editors	Alan G. Bell
Publisher	IEEE
Pages	254-258
Number of pages	5
ISBN (Print)	0818606924
State	Published - Jan 1 1986
Externally published	Yes

Publication series

Name	Proceedings - IEEE Computer Society International Conference

ASJC Scopus subject areas

Engineering(all)

Access to Document

Fingerprint Dive into the research topics of 'EXPERIMENTS WITH HPS, A RESTRICTED DATA FLOW MICROARCHITECTURE FOR HIGH PERFORMANCE COMPUTERS.'. Together they form a unique fingerprint.

Cite this

EXPERIMENTS WITH HPS, A RESTRICTED DATA FLOW MICROARCHITECTURE FOR HIGH PERFORMANCE COMPUTERS. / Patt, Yale; Hwu, Wen mei; Melvin, Stephen; Shebanow, Michael; Chen, Chien; Wei, Jiajuin.

Proceedings - IEEE Computer Society International Conference. ed. / Alan G. Bell. IEEE, 1986. p. 254-258 (Proceedings - IEEE Computer Society International Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

@inproceedings{dd3baadee1f14f40bd16dacf32c58199,

title = "EXPERIMENTS WITH HPS, A RESTRICTED DATA FLOW MICROARCHITECTURE FOR HIGH PERFORMANCE COMPUTERS.",

abstract = "The authors have identified a new model of execution, restricted data flow, which is believed to have great potential for implementing a very-high-performance computing engine. This microengine is called HPS (High Performance Substrate) to reflect the notion that this model should be useful for implementing very dissimilar ISA architectures. Two extreme variations of HPS are specified, a minimal functionality version which can be implemented on a single chip, and a 'full throttle' version which has been proposed as a high performance implementation of the microvax-2 subset of the VAX architecture. Both models have been simulated, and measurements have been taken on several benchmarks. The results of some of these measurements are reported and compared with alternative styles of execution.",

author = "Yale Patt and Hwu, {Wen mei} and Stephen Melvin and Michael Shebanow and Chien Chen and Jiajuin Wei",

year = "1986",

month = jan,

day = "1",

language = "English (US)",

isbn = "0818606924",

series = "Proceedings - IEEE Computer Society International Conference",

publisher = "IEEE",

pages = "254--258",

editor = "Bell, {Alan G.}",

booktitle = "Proceedings - IEEE Computer Society International Conference",

}

TY - GEN

T1 - EXPERIMENTS WITH HPS, A RESTRICTED DATA FLOW MICROARCHITECTURE FOR HIGH PERFORMANCE COMPUTERS.

AU - Patt, Yale

AU - Hwu, Wen mei

AU - Melvin, Stephen

AU - Shebanow, Michael

AU - Chen, Chien

AU - Wei, Jiajuin

PY - 1986/1/1

Y1 - 1986/1/1

N2 - The authors have identified a new model of execution, restricted data flow, which is believed to have great potential for implementing a very-high-performance computing engine. This microengine is called HPS (High Performance Substrate) to reflect the notion that this model should be useful for implementing very dissimilar ISA architectures. Two extreme variations of HPS are specified, a minimal functionality version which can be implemented on a single chip, and a 'full throttle' version which has been proposed as a high performance implementation of the microvax-2 subset of the VAX architecture. Both models have been simulated, and measurements have been taken on several benchmarks. The results of some of these measurements are reported and compared with alternative styles of execution.

AB - The authors have identified a new model of execution, restricted data flow, which is believed to have great potential for implementing a very-high-performance computing engine. This microengine is called HPS (High Performance Substrate) to reflect the notion that this model should be useful for implementing very dissimilar ISA architectures. Two extreme variations of HPS are specified, a minimal functionality version which can be implemented on a single chip, and a 'full throttle' version which has been proposed as a high performance implementation of the microvax-2 subset of the VAX architecture. Both models have been simulated, and measurements have been taken on several benchmarks. The results of some of these measurements are reported and compared with alternative styles of execution.

UR - http://www.scopus.com/inward/record.url?scp=0022593666&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0022593666&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0022593666

SN - 0818606924

T3 - Proceedings - IEEE Computer Society International Conference

SP - 254

EP - 258

BT - Proceedings - IEEE Computer Society International Conference

A2 - Bell, Alan G.

PB - IEEE

ER -