The authors have identified a new model of execution, restricted data flow, which is believed to have great potential for implementing a very-high-performance computing engine. This microengine is called HPS (High Performance Substrate) to reflect the notion that this model should be useful for implementing very dissimilar ISA architectures. Two extreme variations of HPS are specified, a minimal functionality version which can be implemented on a single chip, and a 'full throttle' version which has been proposed as a high performance implementation of the microvax-2 subset of the VAX architecture. Both models have been simulated, and measurements have been taken on several benchmarks. The results of some of these measurements are reported and compared with alternative styles of execution.