EXPERIMENTS WITH HPS, A RESTRICTED DATA FLOW MICROARCHITECTURE FOR HIGH PERFORMANCE COMPUTERS.

Yale Patt, Wen mei Hwu, Stephen Melvin, Michael Shebanow, Chien Chen, Jiajuin Wei

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The authors have identified a new model of execution, restricted data flow, which is believed to have great potential for implementing a very-high-performance computing engine. This microengine is called HPS (High Performance Substrate) to reflect the notion that this model should be useful for implementing very dissimilar ISA architectures. Two extreme variations of HPS are specified, a minimal functionality version which can be implemented on a single chip, and a 'full throttle' version which has been proposed as a high performance implementation of the microvax-2 subset of the VAX architecture. Both models have been simulated, and measurements have been taken on several benchmarks. The results of some of these measurements are reported and compared with alternative styles of execution.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Computer Society International Conference
EditorsAlan G. Bell
PublisherIEEE
Pages254-258
Number of pages5
ISBN (Print)0818606924
StatePublished - Jan 1 1986
Externally publishedYes

Publication series

NameProceedings - IEEE Computer Society International Conference

ASJC Scopus subject areas

  • Engineering(all)

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