Abstract
A methodology is proposed for the quantification and analysis of interconnect-induced noise in semiconductor substrates. The methodology is based on the utilization of commonly-used two-dimensional interconnect parasitics extractors together with SPICE-like simulators. Thus, the proposed model offers a convenient alternative to the use of three-dimensional field solvers for the expedient investigation of the attributes and potential consequences of interconnect-induced substrate noise on on-chip signal integrity.
Original language | English (US) |
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Pages | 269-272 |
Number of pages | 4 |
State | Published - 2004 |
Event | IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging - Portland, OR, United States Duration: Oct 25 2004 → Oct 27 2004 |
Other
Other | IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging |
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Country/Territory | United States |
City | Portland, OR |
Period | 10/25/04 → 10/27/04 |
ASJC Scopus subject areas
- General Engineering