Expedient methodology for the quantification of interconnect-induced semiconductor substrate noise

Research output: Contribution to conferencePaper

Abstract

A methodology is proposed for the quantification and analysis of interconnect-induced noise in semiconductor substrates. The methodology is based on the utilization of commonly-used two-dimensional interconnect parasitics extractors together with SPICE-like simulators. Thus, the proposed model offers a convenient alternative to the use of three-dimensional field solvers for the expedient investigation of the attributes and potential consequences of interconnect-induced substrate noise on on-chip signal integrity.

Original languageEnglish (US)
Pages269-272
Number of pages4
StatePublished - Dec 1 2004
EventIEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging - Portland, OR, United States
Duration: Oct 25 2004Oct 27 2004

Other

OtherIEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging
CountryUnited States
CityPortland, OR
Period10/25/0410/27/04

ASJC Scopus subject areas

  • Engineering(all)

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    Chung, I. J., & Cangellaris, A. C. (2004). Expedient methodology for the quantification of interconnect-induced semiconductor substrate noise. 269-272. Paper presented at IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging, Portland, OR, United States.