Exact tree-based FPGA technology mapping for logic blocks with independent LUTs

Madhukar R. Korupolu, K. K. Lee, D. F. Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution


The logic blocks (CLBs) of a lookup table (LUT) based FPGA consist of one or more LUTs, possibly of different sizes.In this paper,we focus on technology mapping for CLBs with several independent LUTs of two different sizes (called ICLBs).The Actel ES6500 family is an example of a class of commercially available ICLBs.Given a tree network with n nodes, the only previously known approach for minimum area tree-based mapping to ICLBs was a heuristic with running time O(ndS'),where d is the maximum indegree of any node. We give an O(n3)time exact algorithm for mapping a given tree network,an improvement over this heuristic in terms of run time and the solution quality.For general networks, an effective strategy is to break it into trees and combine them.We also give an O(n3)exact algorithm for combining the optimal solutions to these trees, under the condition that LUTs do not go across trees. The method can be extended to solve mapping onto CLBs that can be configured into different ICLBs,(e.g.Xilinx'XC400UE).

Original languageEnglish (US)
Title of host publicationProceedings 1998 - Design and Automation Conference, DAC 1998
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Print)078034409X
StatePublished - 1998
Externally publishedYes
Event35th Design and Automation Conference, DAC 1998 - San Francisco, United States
Duration: Jun 15 1998Jun 19 1998

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


Other35th Design and Automation Conference, DAC 1998
Country/TerritoryUnited States
CitySan Francisco

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation
  • Hardware and Architecture


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