Every test makes a difference

Compressing analog tests to decrease production costs

Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We introduce a methodology for automated test compression during electrical stress testing of analog and mixed signal circuits. This methodology optimally extracts only portions of a functional test that electrically stress the nets and devices of an analog circuit. We model test compression as a problem of optimizing functional of the transient response. We present a random tree based approach to find optimal solutions for these computationally hard integrals. We demonstrate with an op-amp, VCO and CMOS inverter that the method consistently reduces the length of each test by an average of 93%.

Original languageEnglish (US)
Title of host publication2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages539-544
Number of pages6
ISBN (Electronic)9781467395694
DOIs
StatePublished - Mar 7 2016
Event21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 - Macao, Macao
Duration: Jan 25 2016Jan 28 2016

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume25-28-January-2016

Other

Other21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
CountryMacao
CityMacao
Period1/25/161/28/16

Fingerprint

Operational amplifiers
Variable frequency oscillators
Analog circuits
Transient analysis
Costs
Networks (circuits)
Testing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

Ahmadyan, S. N., Natarajan, S., & Vasudevan, S. (2016). Every test makes a difference: Compressing analog tests to decrease production costs. In 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 (pp. 539-544). [7428067] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 25-28-January-2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2016.7428067

Every test makes a difference : Compressing analog tests to decrease production costs. / Ahmadyan, Seyed Nematollah; Natarajan, Suriyaprakash; Vasudevan, Shobha.

2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 539-544 7428067 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 25-28-January-2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ahmadyan, SN, Natarajan, S & Vasudevan, S 2016, Every test makes a difference: Compressing analog tests to decrease production costs. in 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016., 7428067, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 25-28-January-2016, Institute of Electrical and Electronics Engineers Inc., pp. 539-544, 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016, Macao, Macao, 1/25/16. https://doi.org/10.1109/ASPDAC.2016.7428067
Ahmadyan SN, Natarajan S, Vasudevan S. Every test makes a difference: Compressing analog tests to decrease production costs. In 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 539-544. 7428067. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2016.7428067
Ahmadyan, Seyed Nematollah ; Natarajan, Suriyaprakash ; Vasudevan, Shobha. / Every test makes a difference : Compressing analog tests to decrease production costs. 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 539-544 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).
@inproceedings{3eda438185d74e95ad75014364cb8992,
title = "Every test makes a difference: Compressing analog tests to decrease production costs",
abstract = "We introduce a methodology for automated test compression during electrical stress testing of analog and mixed signal circuits. This methodology optimally extracts only portions of a functional test that electrically stress the nets and devices of an analog circuit. We model test compression as a problem of optimizing functional of the transient response. We present a random tree based approach to find optimal solutions for these computationally hard integrals. We demonstrate with an op-amp, VCO and CMOS inverter that the method consistently reduces the length of each test by an average of 93{\%}.",
author = "Ahmadyan, {Seyed Nematollah} and Suriyaprakash Natarajan and Shobha Vasudevan",
year = "2016",
month = "3",
day = "7",
doi = "10.1109/ASPDAC.2016.7428067",
language = "English (US)",
series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "539--544",
booktitle = "2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016",
address = "United States",

}

TY - GEN

T1 - Every test makes a difference

T2 - Compressing analog tests to decrease production costs

AU - Ahmadyan, Seyed Nematollah

AU - Natarajan, Suriyaprakash

AU - Vasudevan, Shobha

PY - 2016/3/7

Y1 - 2016/3/7

N2 - We introduce a methodology for automated test compression during electrical stress testing of analog and mixed signal circuits. This methodology optimally extracts only portions of a functional test that electrically stress the nets and devices of an analog circuit. We model test compression as a problem of optimizing functional of the transient response. We present a random tree based approach to find optimal solutions for these computationally hard integrals. We demonstrate with an op-amp, VCO and CMOS inverter that the method consistently reduces the length of each test by an average of 93%.

AB - We introduce a methodology for automated test compression during electrical stress testing of analog and mixed signal circuits. This methodology optimally extracts only portions of a functional test that electrically stress the nets and devices of an analog circuit. We model test compression as a problem of optimizing functional of the transient response. We present a random tree based approach to find optimal solutions for these computationally hard integrals. We demonstrate with an op-amp, VCO and CMOS inverter that the method consistently reduces the length of each test by an average of 93%.

UR - http://www.scopus.com/inward/record.url?scp=84996721545&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84996721545&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2016.7428067

DO - 10.1109/ASPDAC.2016.7428067

M3 - Conference contribution

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 539

EP - 544

BT - 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016

PB - Institute of Electrical and Electronics Engineers Inc.

ER -