Evaluation of design options for the trace cache fetch mechanism

Sanjay Jeram Patel, Daniel Holmes Friendly, Yale N. Patt

Research output: Contribution to journalReview articlepeer-review


In this paper, we examine some critical design features of a trace cache fetch engine for a 16-wide issue processor and evaluate their effects on performance. We evaluate path associativity, partial matching, and inactive issue, all of which are straightforward extensions to the trace cache. We examine features such as the fill unit and branch predictor design. In our final analysis, we show that the trace cache mechanism attains a 28 percent performance improvement over an aggressive single block fetch mechanism and a 15 percent improvement over a sequential multiblock mechanism.

Original languageEnglish (US)
Pages (from-to)193-204
Number of pages12
JournalIEEE Transactions on Computers
Issue number2
StatePublished - 1999
Externally publishedYes


  • High bandwidth fetch mechanisms
  • Instruction cache
  • Speculative execution
  • Trace cache
  • Wide issue machines

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics


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