Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench

Keyphrases

• OpenCL 100%
• Irregular Memory Access 100%
• FPGA Platform 100%
• XSBench 100%
• Scientific Computing 40%
• Irregular Memory Access Patterns 40%
• High Performance 20%
• Monte Carlo Code 20%
• On-chip Memory 20%
• Intel 20%
• High-level Synthesis Tools 20%
• Floating-point 20%
• Optimization Strategy 20%
• Study Optimization 20%
• High Energy Efficiency 20%
• Heterogeneous Computing 20%
• Intel Xeon Phi 20%
• FPGA Programming 20%
• Altera 20%
• Optimized Architecture 20%
• FPGA Design 20%
• Synthesis Flow 20%
• Energy Characteristics 20%
• Automated Synthesis 20%
• Computing Unit 20%
• Streamlined Flows 20%

Computer Science

• Case Study 100%
• Memory Access 100%
• OpenCL 100%
• Memory Access Pattern 40%
• Monte Carlo Simulation 20%
• Synthesis Tool 20%
• High Level Synthesis 20%
• Energy Efficiency 20%
• Floating Point 20%
• Simulation Code 20%
• Optimization Strategy 20%
• Heterogeneous Computation 20%
• Energy Performance 20%
• Computing Units 20%