ETS-A: A new electrothermal simulator for CMOS VLSI circuits

Yi Kan Cheng, Elyse Rosenbaum, Sung Mo Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In view of the increasing density on integrated circuit devices for higher operation speed and larger scale of integration, the power density and the resulting temperature on the chip surface increase accordingly. In order to predict the temperature profile as well as the corresponding electrical performance of VLSI circuits, a new electrothermal simulator was developed. By automating the layout extraction, accurate fast timing-based power calculation, the analytical temperature estimation, and the uncoupled electrothermal simulation, the on-chip thermal reliability and timing problems can be accurately and quickly predicted.

Original languageEnglish (US)
Title of host publicationProceedings of the 1996 European Conference on Design and Test, EDTC 1996
PublisherAssociation for Computing Machinery, Inc
Pages566-570
Number of pages5
ISBN (Electronic)0818674237, 9780818674235
DOIs
StatePublished - Mar 11 1996
Event1996 European Conference on Design and Test, EDTC 1996 - Paris, France
Duration: Mar 11 1996Mar 14 1996

Publication series

NameProceedings of the 1996 European Conference on Design and Test, EDTC 1996

Other

Other1996 European Conference on Design and Test, EDTC 1996
CountryFrance
CityParis
Period3/11/963/14/96

ASJC Scopus subject areas

  • Safety, Risk, Reliability and Quality
  • Electrical and Electronic Engineering
  • Hardware and Architecture

Fingerprint Dive into the research topics of 'ETS-A: A new electrothermal simulator for CMOS VLSI circuits'. Together they form a unique fingerprint.

Cite this