ESD/EOS Protection Circuits For Integrated Circuits

Sung Mo (Steve) Kang (Inventor), Carlos H Diaz (Inventor), Charvaka Duvvury (Inventor)

Research output: Patent


An ESD/EOS protection circuit 10. Trigger nMOS transistor M1 has a drain 20 connected to a voltage pad 22, a gate 24 connected to ground 26 and a source 28 connected to ground 26 through source resistor R.sub.e. Switch control nMOS transistor M2 has a drain 30, a gate 34 connected to source 28 of transistor M1, and a source 38 connected to ground 26. Current controlled switch (CCS) 40 is connected to voltage pad 22, ground 26 and drain 30 of transistor M2. CCS 40 is a bipolar pnp-based current controlled switch.
Original languageEnglish (US)
U.S. patent number5450267
Filing date3/31/93
StatePublished - Sep 12 1995


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