ESD time-domain characterization of high-k gate dielectric in a 32 nm CMOS technology

James Di Sarro; Yang Yang; Kiran Chatty; Robert Gauthier; Adrien Ille; Souvick Mitra; Junjun Li; Christian Russ; Elyse Rosenbaum; Dimitris Ioannou

ESD time-domain characterization of high-k gate dielectric in a 32 nm CMOS technology

James Di Sarro, Yang Yang, Kiran Chatty, Robert Gauthier, Adrien Ille, Souvick Mitra, Junjun Li, Christian Russ, Elyse Rosenbaum, Dimitris Ioannou

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Gate dielectric breakdown measurements were performed on high-k/metal gate and SiON/polysilicon gate NMOSFETs down to the ESD time domain. Measurements indicate that, for a given NMOSFET on-state performance level, high-k transistors have increased robustness to ESD compared to SiON transistors.

Original language	English (US)
Title of host publication	Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2009, EOS/ESD 2009
State	Published - 2009
Event	Electrical Overstress/Electrostatic Discharge Symposium 2009, EOS/ESD 2009 - Anaheim, CA, United States Duration: Aug 30 2009 → Sep 4 2009

Publication series

Name	Electrical Overstress/Electrostatic Discharge Symposium Proceedings
ISSN (Print)	0739-5159

Other

Other	Electrical Overstress/Electrostatic Discharge Symposium 2009, EOS/ESD 2009
Country/Territory	United States
City	Anaheim, CA
Period	8/30/09 → 9/4/09

ASJC Scopus subject areas

Electrical and Electronic Engineering

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Di Sarro, J., Yang, Y., Chatty, K., Gauthier, R., Ille, A., Mitra, S., Li, J., Russ, C., Rosenbaum, E., & Ioannou, D. (2009). ESD time-domain characterization of high-k gate dielectric in a 32 nm CMOS technology. In Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2009, EOS/ESD 2009 Article 5340124 (Electrical Overstress/Electrostatic Discharge Symposium Proceedings).

ESD time-domain characterization of high-k gate dielectric in a 32 nm CMOS technology. / Di Sarro, James; Yang, Yang; Chatty, Kiran et al.
Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2009, EOS/ESD 2009. 2009. 5340124 (Electrical Overstress/Electrostatic Discharge Symposium Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Di Sarro, J, Yang, Y, Chatty, K, Gauthier, R, Ille, A, Mitra, S, Li, J, Russ, C, Rosenbaum, E & Ioannou, D 2009, ESD time-domain characterization of high-k gate dielectric in a 32 nm CMOS technology. in Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2009, EOS/ESD 2009., 5340124, Electrical Overstress/Electrostatic Discharge Symposium Proceedings, Electrical Overstress/Electrostatic Discharge Symposium 2009, EOS/ESD 2009, Anaheim, CA, United States, 8/30/09.

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title = "ESD time-domain characterization of high-k gate dielectric in a 32 nm CMOS technology",

abstract = "Gate dielectric breakdown measurements were performed on high-k/metal gate and SiON/polysilicon gate NMOSFETs down to the ESD time domain. Measurements indicate that, for a given NMOSFET on-state performance level, high-k transistors have increased robustness to ESD compared to SiON transistors.",

author = "{Di Sarro}, James and Yang Yang and Kiran Chatty and Robert Gauthier and Adrien Ille and Souvick Mitra and Junjun Li and Christian Russ and Elyse Rosenbaum and Dimitris Ioannou",

year = "2009",

language = "English (US)",

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AU - Di Sarro, James

AU - Yang, Yang

AU - Chatty, Kiran

AU - Gauthier, Robert

AU - Ille, Adrien

AU - Mitra, Souvick

AU - Li, Junjun

AU - Russ, Christian

AU - Rosenbaum, Elyse

AU - Ioannou, Dimitris

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N2 - Gate dielectric breakdown measurements were performed on high-k/metal gate and SiON/polysilicon gate NMOSFETs down to the ESD time domain. Measurements indicate that, for a given NMOSFET on-state performance level, high-k transistors have increased robustness to ESD compared to SiON transistors.

AB - Gate dielectric breakdown measurements were performed on high-k/metal gate and SiON/polysilicon gate NMOSFETs down to the ESD time domain. Measurements indicate that, for a given NMOSFET on-state performance level, high-k transistors have increased robustness to ESD compared to SiON transistors.

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AN - SCOPUS:77950982538

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T3 - Electrical Overstress/Electrostatic Discharge Symposium Proceedings

BT - Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2009, EOS/ESD 2009

T2 - Electrical Overstress/Electrostatic Discharge Symposium 2009, EOS/ESD 2009

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ESD time-domain characterization of high-k gate dielectric in a 32 nm CMOS technology

Abstract

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