ESD robustness prediction and protection device design in partially depleted SOI technology

P. Raha, J. C. Smith, J. W. Miller, E. Rosenbaum

Research output: Contribution to journalArticle

Abstract

In this paper we investigate and develop models for partially-depleted silicon-on-insulator (SOI) (PD-SOI) device failure under EOS/ESD stress. The model and experimental data show that due to increased device self-heating, the second-breakdown current per micron width (It2) for salicided PD-SOI metal-oxide semiconductor field effect transistor (MOSFET)s with Si film thickness of 100 nm is about 50% of that in their bulk counterparts under human body model (HBM-ESD) stress pulses. Furthermore, It2 did not scale with device width. Therefore, ESD protection devices with non-silicided S/D diffusions and source-body tied MOSFETs are investigated for improved ESD protection levels. Compact ESD protection networks using the source-body tied device may have been shown to achieve HBM-ESD protection levels of +3.75 kV (Smith JC, Lien M, Veeraghaven S. An ESD protection circuit for TFSOI technology. International SOI Conf. Proc. 1996. pp. 170-71).

Original languageEnglish (US)
Pages (from-to)1723-1731
Number of pages9
JournalMicroelectronics Reliability
Volume38
Issue number11
DOIs
StatePublished - Jan 1 1998

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Safety, Risk, Reliability and Quality
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

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