ESD robustness prediction and protection device design in partially depleted SOI technology

P. Raha; J. C. Smith; J. W. Miller; E. Rosenbaum

doi:10.1016/S0026-2714(98)00175-9

ESD robustness prediction and protection device design in partially depleted SOI technology

P. Raha, J. C. Smith, J. W. Miller, E. Rosenbaum

Research output: Contribution to journal › Article › peer-review

Abstract

In this paper we investigate and develop models for partially-depleted silicon-on-insulator (SOI) (PD-SOI) device failure under EOS/ESD stress. The model and experimental data show that due to increased device self-heating, the second-breakdown current per micron width (I_t2) for salicided PD-SOI metal-oxide semiconductor field effect transistor (MOSFET)s with Si film thickness of 100 nm is about 50% of that in their bulk counterparts under human body model (HBM-ESD) stress pulses. Furthermore, I_t2 did not scale with device width. Therefore, ESD protection devices with non-silicided S/D diffusions and source-body tied MOSFETs are investigated for improved ESD protection levels. Compact ESD protection networks using the source-body tied device may have been shown to achieve HBM-ESD protection levels of +3.75 kV (Smith JC, Lien M, Veeraghaven S. An ESD protection circuit for TFSOI technology. International SOI Conf. Proc. 1996. pp. 170-71).

Original language	English (US)
Pages (from-to)	1723-1731
Number of pages	9
Journal	Microelectronics Reliability
Volume	38
Issue number	11
DOIs	https://doi.org/10.1016/S0026-2714(98)00175-9
State	Published - 1998

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Safety, Risk, Reliability and Quality
Surfaces, Coatings and Films
Atomic and Molecular Physics, and Optics
Electrical and Electronic Engineering

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10.1016/S0026-2714(98)00175-9

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title = "ESD robustness prediction and protection device design in partially depleted SOI technology",

abstract = "In this paper we investigate and develop models for partially-depleted silicon-on-insulator (SOI) (PD-SOI) device failure under EOS/ESD stress. The model and experimental data show that due to increased device self-heating, the second-breakdown current per micron width (It2) for salicided PD-SOI metal-oxide semiconductor field effect transistor (MOSFET)s with Si film thickness of 100 nm is about 50% of that in their bulk counterparts under human body model (HBM-ESD) stress pulses. Furthermore, It2 did not scale with device width. Therefore, ESD protection devices with non-silicided S/D diffusions and source-body tied MOSFETs are investigated for improved ESD protection levels. Compact ESD protection networks using the source-body tied device may have been shown to achieve HBM-ESD protection levels of +3.75 kV (Smith JC, Lien M, Veeraghaven S. An ESD protection circuit for TFSOI technology. International SOI Conf. Proc. 1996. pp. 170-71).",

author = "P. Raha and Smith, {J. C.} and Miller, {J. W.} and E. Rosenbaum",

note = "Funding Information: This research was supported by the Joint Services Electronics Program under contract number N00014-96-1-0129, and the National Science Foundation. The authors would also like to thank TMA for donating the MEDICI software. Copyright: Copyright 2017 Elsevier B.V., All rights reserved.",

year = "1998",

doi = "10.1016/S0026-2714(98)00175-9",

language = "English (US)",

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T1 - ESD robustness prediction and protection device design in partially depleted SOI technology

AU - Raha, P.

AU - Smith, J. C.

AU - Miller, J. W.

AU - Rosenbaum, E.

N1 - Funding Information: This research was supported by the Joint Services Electronics Program under contract number N00014-96-1-0129, and the National Science Foundation. The authors would also like to thank TMA for donating the MEDICI software. Copyright: Copyright 2017 Elsevier B.V., All rights reserved.

PY - 1998

Y1 - 1998

N2 - In this paper we investigate and develop models for partially-depleted silicon-on-insulator (SOI) (PD-SOI) device failure under EOS/ESD stress. The model and experimental data show that due to increased device self-heating, the second-breakdown current per micron width (It2) for salicided PD-SOI metal-oxide semiconductor field effect transistor (MOSFET)s with Si film thickness of 100 nm is about 50% of that in their bulk counterparts under human body model (HBM-ESD) stress pulses. Furthermore, It2 did not scale with device width. Therefore, ESD protection devices with non-silicided S/D diffusions and source-body tied MOSFETs are investigated for improved ESD protection levels. Compact ESD protection networks using the source-body tied device may have been shown to achieve HBM-ESD protection levels of +3.75 kV (Smith JC, Lien M, Veeraghaven S. An ESD protection circuit for TFSOI technology. International SOI Conf. Proc. 1996. pp. 170-71).

AB - In this paper we investigate and develop models for partially-depleted silicon-on-insulator (SOI) (PD-SOI) device failure under EOS/ESD stress. The model and experimental data show that due to increased device self-heating, the second-breakdown current per micron width (It2) for salicided PD-SOI metal-oxide semiconductor field effect transistor (MOSFET)s with Si film thickness of 100 nm is about 50% of that in their bulk counterparts under human body model (HBM-ESD) stress pulses. Furthermore, It2 did not scale with device width. Therefore, ESD protection devices with non-silicided S/D diffusions and source-body tied MOSFETs are investigated for improved ESD protection levels. Compact ESD protection networks using the source-body tied device may have been shown to achieve HBM-ESD protection levels of +3.75 kV (Smith JC, Lien M, Veeraghaven S. An ESD protection circuit for TFSOI technology. International SOI Conf. Proc. 1996. pp. 170-71).

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ESD robustness prediction and protection device design in partially depleted SOI technology

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