ESD-resilient active biasing scheme for high-speed SSTL I/Os

Keyphrases

• Resilient 100%
• Biasing Scheme 100%
• Active Biasing 100%
• Transistor 50%
• Gate Oxide 50%
• Resilience 50%
• Control Circuit 50%
• Source Area 50%
• Circuit Performance 50%
• Peak Voltage 50%
• ESD Events 50%
• Bias Control 50%
• Active Bias 50%

Engineering

• Gate Oxide 100%
• Source Region 100%
• Circuit Performance 100%