ESD-resilient active biasing scheme for high-speed SSTL I/Os

Min Sun Keel, Nathan Jack, Elyse Rosenbaum

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A bidirectional SSTL I/O which utilizes an active-biasing technique to achieve enhanced ESD resilience is presented. During an ESD event, each vulnerable transistor has an appropriate bias applied to minimize the peak voltage across gate oxide and drain-source regions. Active-bias control circuits can be substituted for secondary protection to improve circuit performance and ESD reliability.

Original languageEnglish (US)
Title of host publicationElectrical Overstress/Electrostatic Discharge Symposium Proceedings, EOS/ESD 2013
StatePublished - Oct 16 2013
Event2013 35th Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2013 - Las Vegas, NV, United States
Duration: Sep 8 2013Sep 13 2013

Publication series

NameElectrical Overstress/Electrostatic Discharge Symposium Proceedings
ISSN (Print)0739-5159

Other

Other2013 35th Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2013
CountryUnited States
CityLas Vegas, NV
Period9/8/139/13/13

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Keel, M. S., Jack, N., & Rosenbaum, E. (2013). ESD-resilient active biasing scheme for high-speed SSTL I/Os. In Electrical Overstress/Electrostatic Discharge Symposium Proceedings, EOS/ESD 2013 [6635906] (Electrical Overstress/Electrostatic Discharge Symposium Proceedings).