ESD protection networks for 3D integrated circuits

Elyse Rosenbaum, Vrashank Shukla, Min Sun Keel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The inter-die signal interfaces in a 3D-IC are vulnerable to over-voltage stress induced by Charged Device Model ESD. The magnitude of the stress is highly sensitive to the design of the ground distribution network on both the die and package level. It is also affected by the type of package being used. Small voltage clamping devices may be placed at inter-die receivers to mitigate the risk of gate dielectric breakdown. New ESD rule checking tools are needed for 3D-IC design automation.

Original languageEnglish (US)
Title of host publication2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
DOIs
StatePublished - Dec 1 2011
Event2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 - Osaka, Japan
Duration: Jan 31 2012Feb 2 2012

Publication series

Name2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

Other

Other2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
CountryJapan
CityOsaka
Period1/31/122/2/12

Keywords

  • Charged Device Model
  • Electrostatic discharge

ASJC Scopus subject areas

  • Control and Systems Engineering

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