TY - GEN
T1 - ESD protection for high-speed receiver circuits
AU - Jack, Nathan
AU - Rosenbaum, Elyse
PY - 2010/10/20
Y1 - 2010/10/20
N2 - ESD-induced gate oxide breakdown is studied in highspeed receiver circuits. A novel biasing circuit increases the breakdown voltage by modulating the potential of the input transistor's source during ESD. The effectiveness of dual-diode and DTSCR protection of high-speed receiver circuits is examined under various bias conditions.
AB - ESD-induced gate oxide breakdown is studied in highspeed receiver circuits. A novel biasing circuit increases the breakdown voltage by modulating the potential of the input transistor's source during ESD. The effectiveness of dual-diode and DTSCR protection of high-speed receiver circuits is examined under various bias conditions.
UR - http://www.scopus.com/inward/record.url?scp=77957923042&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77957923042&partnerID=8YFLogxK
U2 - 10.1109/IRPS.2010.5488722
DO - 10.1109/IRPS.2010.5488722
M3 - Conference contribution
AN - SCOPUS:77957923042
SN - 9781424454310
T3 - IEEE International Reliability Physics Symposium Proceedings
SP - 835
EP - 840
BT - 2010 IEEE International Reliability Physics Symposium, IRPS 2010
T2 - 2010 IEEE International Reliability Physics Symposium, IRPS 2010
Y2 - 2 May 2010 through 6 May 2010
ER -