ESD protection for high-speed receiver circuits

Nathan Jack, Elyse Rosenbaum

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

ESD-induced gate oxide breakdown is studied in highspeed receiver circuits. A novel biasing circuit increases the breakdown voltage by modulating the potential of the input transistor's source during ESD. The effectiveness of dual-diode and DTSCR protection of high-speed receiver circuits is examined under various bias conditions.

Original languageEnglish (US)
Title of host publication2010 IEEE International Reliability Physics Symposium, IRPS 2010
Pages835-840
Number of pages6
DOIs
StatePublished - Oct 20 2010
Event2010 IEEE International Reliability Physics Symposium, IRPS 2010 - Garden Grove, CA, Canada
Duration: May 2 2010May 6 2010

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026

Other

Other2010 IEEE International Reliability Physics Symposium, IRPS 2010
CountryCanada
CityGarden Grove, CA
Period5/2/105/6/10

ASJC Scopus subject areas

  • Engineering(all)

Fingerprint Dive into the research topics of 'ESD protection for high-speed receiver circuits'. Together they form a unique fingerprint.

  • Cite this

    Jack, N., & Rosenbaum, E. (2010). ESD protection for high-speed receiver circuits. In 2010 IEEE International Reliability Physics Symposium, IRPS 2010 (pp. 835-840). [5488722] (IEEE International Reliability Physics Symposium Proceedings). https://doi.org/10.1109/IRPS.2010.5488722