This paper provides an overview of error-resilient techniques to design robust and energy-efficient nanoscale DSP systems while focusing on statistical error compensation techniques. We demonstrate that logic-level error resiliency devises techniques independent of the application context. This results in significant complexity overhead especially with the highly unreliable circuits fabric. On the other hand, system-level error resiliency, such as statistical error compensation, employs techniques from statistical signal processing in order to exploit the hardware error behavior at application level and engineer the error compensation mechanism to match the application requirements. The benefits of such a design philosophy are tremendous gains in robustness (> 1000×) and energy efficiency (3×-to-6×). In addition, the paper paves the way to the deployment of novel statistical error compensation techniques based on principles from pattern recognition and iterative/turbo detection.