Error-resilient systems via statistical signal processing

Rami A. Abdallah, Naresh R. Shanbhag

Research output: Chapter in Book/Report/Conference proceedingConference contribution


This paper provides an overview of error-resilient techniques to design robust and energy-efficient nanoscale DSP systems while focusing on statistical error compensation techniques. We demonstrate that logic-level error resiliency devises techniques independent of the application context. This results in significant complexity overhead especially with the highly unreliable circuits fabric. On the other hand, system-level error resiliency, such as statistical error compensation, employs techniques from statistical signal processing in order to exploit the hardware error behavior at application level and engineer the error compensation mechanism to match the application requirements. The benefits of such a design philosophy are tremendous gains in robustness (> 1000×) and energy efficiency (3×-to-6×). In addition, the paper paves the way to the deployment of novel statistical error compensation techniques based on principles from pattern recognition and iterative/turbo detection.

Original languageEnglish (US)
Title of host publication2013 IEEE Workshop on Signal Processing Systems, SiPS 2013
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Print)9781467362382
StatePublished - 2013
Event2013 IEEE Workshop on Signal Processing Systems, SiPS 2013 - Taipei, Taiwan, Province of China
Duration: Oct 16 2013Oct 18 2013

Publication series

NameIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)1520-6130


Other2013 IEEE Workshop on Signal Processing Systems, SiPS 2013
Country/TerritoryTaiwan, Province of China


  • Error resiliency
  • Low power
  • Statistical error compensation
  • Voltage overscaling

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing
  • Applied Mathematics
  • Hardware and Architecture


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