Abstract
The energy and delay reductions from CMOS scaling have stagnated, motivating the search for a CMOS replacement. Spintronic devices are one of the promising beyond-CMOS alternatives. However, they exhibit high switching error rates of 1% or more when operated at energy and delay comparable to CMOS, rendering them incompatible with the deterministic nature of digital implementations. In this paper, we employ a Shannon-inspired model of computation to enhance the tolerance of all-spin logic (ASL)-based implementations to gate-level switching errors. We develop the logic-level path delay reallocation techniques to shape the output error statistics and propose a novel error compensation scheme to achieve 1000\times higher tolerance to device-level switching errors while maintaining the classification accuracy of an ASL-based support vector machine (SVM) classifier.
Original language | English (US) |
---|---|
Article number | 8689353 |
Pages (from-to) | 10-18 |
Number of pages | 9 |
Journal | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
Volume | 5 |
Issue number | 1 |
DOIs | |
State | Published - Jun 2019 |
Keywords
- All spin logic
- beyond-CMOS
- machine learning
- spintronics
- statistical computing
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
- Hardware and Architecture