Error-Resilient Spintronics via the Shannon- Inspired Model of Computation

Ameya D. Patil, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young, Naresh R. Shanbhag

Research output: Contribution to journalArticlepeer-review


The energy and delay reductions from CMOS scaling have stagnated, motivating the search for a CMOS replacement. Spintronic devices are one of the promising beyond-CMOS alternatives. However, they exhibit high switching error rates of 1% or more when operated at energy and delay comparable to CMOS, rendering them incompatible with the deterministic nature of digital implementations. In this paper, we employ a Shannon-inspired model of computation to enhance the tolerance of all-spin logic (ASL)-based implementations to gate-level switching errors. We develop the logic-level path delay reallocation techniques to shape the output error statistics and propose a novel error compensation scheme to achieve 1000\times higher tolerance to device-level switching errors while maintaining the classification accuracy of an ASL-based support vector machine (SVM) classifier.

Original languageEnglish (US)
Article number8689353
Pages (from-to)10-18
Number of pages9
JournalIEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Issue number1
StatePublished - Jun 2019


  • All spin logic
  • beyond-CMOS
  • machine learning
  • spintronics
  • statistical computing

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials


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