Error-resilient motion estimation architecture

Girish Vishnu Varatkar, Naresh R. Shanbhag

Research output: Contribution to journalArticle

Abstract

In this paper, we propose an energy-efficient motion estimation architecture. The proposed architecture employs the principle of error-resiliency to combat logic level timing errors that may arise in average-case designs in presence of process variations and/or due to overscaling of the supply voltage [voltage overscaling (VOS)] and thereby achieves power reduction. Error-resiliency is incorporated via algorithmic noise-tolerance (ANT). Referred to as input subsampled replica ANT (ISR-ANT), the proposed technique incorporates an input subsampled replica of the main sum-of-absolute-difference (MSAD) block for detecting and correcting errors in the MSAD block. Simulations show that the proposed technique can save up to 60% power over an optimal error-free system in a 130-nm CMOS technology. These power savings increase to 78% in a 45-nm predictive process technology. Performance of the ISR-ANT architecture in the presence of process variations indicates that average peak signal-to-noise ratio (PSNR) of the ISR-ANT architecture increases by up to 1.8 dB over that of the conventional architecture in 130-nm IBM process technology. Furthermore, the PSNR variation (σ/μ) is also reduced by 7× over that of the conventional architecture at the slow corner while achieving a power reduction of 33%.

Original languageEnglish (US)
Article number4629348
Pages (from-to)1399-1412
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume16
Issue number10
DOIs
StatePublished - Oct 1 2008

Keywords

  • Algorithmic noise-tolerance
  • Error-tolerant design
  • Low power design
  • Motion estimation
  • Process variation-tolerance

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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