Error-resilient low-power viterbi decoders via state clustering

Rami A. Abdallah, Naresh R. Shanbhag

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Low-power Viterbi decoder (VD) architectures based on the principle of error-resiliency are presented in this paper. Power reduction in the add-compare-select units (ACSUs) of a VD is achieved by either overscaling the supply voltage (voltage overscaling (VOS)) or designing at the nominal process corner and supply voltage (average-case design). In either case, the data-dependent timing errors which occur whenever a critical path is excited, are corrected via the application of algorithmic noise-tolerance (ANT). The concept of state clustering is employed to develop efficient estimators for error-correction. Power savings achieved in the presence of VOS and process variations are 71% and 62%, respectively, at a loss of 0.8 dB and 0.6 dB in coding gain in a IBM 130nm CMOS process.

Original languageEnglish (US)
Title of host publication2008 IEEE Workshop on Signal Processing Systems, SiPS 2008, Proceedings
Pages221-226
Number of pages6
DOIs
StatePublished - Dec 26 2008
Event2008 IEEE Workshop on Signal Processing Systems, SiPS 2008 - Washington, DC, United States
Duration: Oct 8 2008Oct 10 2008

Publication series

NameIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)1520-6130

Other

Other2008 IEEE Workshop on Signal Processing Systems, SiPS 2008
Country/TerritoryUnited States
CityWashington, DC
Period10/8/0810/10/08

Keywords

  • Algorithmic noise tolerance
  • Error resiliency
  • Process variations
  • Viterbi decoder
  • Voltage overscaling

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing
  • Applied Mathematics
  • Hardware and Architecture

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