@inproceedings{e3813fa5a700469096f18318be8d2209,
title = "Error-resilient low-power viterbi decoders via state clustering",
abstract = "Low-power Viterbi decoder (VD) architectures based on the principle of error-resiliency are presented in this paper. Power reduction in the add-compare-select units (ACSUs) of a VD is achieved by either overscaling the supply voltage (voltage overscaling (VOS)) or designing at the nominal process corner and supply voltage (average-case design). In either case, the data-dependent timing errors which occur whenever a critical path is excited, are corrected via the application of algorithmic noise-tolerance (ANT). The concept of state clustering is employed to develop efficient estimators for error-correction. Power savings achieved in the presence of VOS and process variations are 71% and 62%, respectively, at a loss of 0.8 dB and 0.6 dB in coding gain in a IBM 130nm CMOS process.",
keywords = "Algorithmic noise tolerance, Error resiliency, Process variations, Viterbi decoder, Voltage overscaling",
author = "Abdallah, {Rami A.} and Shanbhag, {Naresh R.}",
year = "2008",
doi = "10.1109/SIPS.2008.4671766",
language = "English (US)",
isbn = "9781424429240",
series = "IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation",
pages = "221--226",
booktitle = "2008 IEEE Workshop on Signal Processing Systems, SiPS 2008, Proceedings",
note = "2008 IEEE Workshop on Signal Processing Systems, SiPS 2008 ; Conference date: 08-10-2008 Through 10-10-2008",
}