Error-resilient low-power Viterbi decoders

Rami A. Abdallah, Naresh R Shanbhag

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Two low-power Viterbi decoder (VD) architectures are presented in this paper. In the first, limited decision errors are introduced in the add-compare-select units (ACSUs) of a VD to reduce their critical path delays so that they can be operated at lower supply voltages in absence of timing errors. In the second one, we allow data-dependent timing errors which occur whenever a critical path in the ACSU is excited. Algorithmic noise-tolerance (ANT) is then applied at the level of the ACSU to correct for these errors. Power reduction in this design is achieved by either overscaling the supply voltage (voltage overscaling (VOS)) or designing at the nominal process corner and supply voltage (average-case design). Power savings in the first and second design are 58% and 40% at a coding loss of 0.15 dB and 1.1 dB respectively in a IBM 130nm CMOS process.

Original languageEnglish (US)
Title of host publicationISLPED'08
Subtitle of host publicationProceedings of the 2008 International Symposium on Low Power Electronics and Design
Pages111-116
Number of pages6
DOIs
StatePublished - Dec 17 2008
EventISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design - Bangalore, India
Duration: Aug 11 2008Aug 13 2008

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

OtherISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design
CountryIndia
CityBangalore
Period8/11/088/13/08

Keywords

  • Algorithms
  • Design
  • Performance
  • Reliability

ASJC Scopus subject areas

  • Engineering(all)

Fingerprint Dive into the research topics of 'Error-resilient low-power Viterbi decoders'. Together they form a unique fingerprint.

Cite this