Error-resilient low-power viterbi decoder architectures

Three low-power Viterbi decoder (VD) architectures are presented in this paper. In the first, limited decision errors are introduced in the add-compare-select units (ACSUs) of a VD to reduce their critical path delays so that they can be operated at lower supply voltages without incurring timing errors. Power savings in this design can reach 58% and 44% with a 0.15 dB coding loss under reduced voltage operation and process variations, respectively, with adaptive supply voltage and adaptive body biasing applied to avoid timing errors. In the other two designs, we permit data-dependent timing errors to occur whenever a critical path in the ACSU is excited. Algorithmic noise-tolerance (ANT) is then applied to correct for these errors. Power reduction in these schemes is achieved by either overscaling the supply voltage [voltage overscaling (VOS)] or designing at the nominal process corner and supply voltage (average-case design). Two techniques are proposed to develop efficient estimators for error-correction and achieving increased robustness to timing based errors. The first is based on reduced-precision redundancy and the second on state clustering. The first can achieve up to 40% and 25% power savings under VOS and process variations with loss in coding gain of 1.1 and 1.2 dB, respectively, in a 130-nm CMOS process. The second can achieve up to 71% and 62% power savings under VOS and process variations, respectively, at a loss in coding gain of 0.8 and 0.6 dB, respectively. Under process variations, the designs achieve 16-33X improvement in bit error-rate (BER) performance at a signal-to-noise ratio (SNR) of 2 dB.