Abstract
A process flow for the heterogeneous integration of III-V epitaxial material onto a silicon host wafer using CMOS-compatible materials and methods toward the goal of forming electronic-photonic circuitry is presented. Epitaxial structures for compoundsemiconductor- based transistors are assembled on a silicon carrier wafer using a commercially-available polymer and then formed into distinct patterns for scalable processing. A CMOS-compatible metallization process is performed on the back side collector terminal of the aligned epitaxial structures, followed by a metal-eutectic bonding process that transfers the wafer-scale array of III-V material onto a separate silicon host wafer allowing the fabrication of both electronic and photonic devices on a single wafer. Characterization of the epitaxial bonding and transfer is performed to ensure material alignment is maintained without additional tooling and that the interconnect layer established between III-V collector and silicon host wafer performs as an ohmic contact, thermal path, and mechanical bond compatible with back-end-of-line (BEOL) integrated circuit processing. These processes are shown for GaAs-based light-emitting transistor (LET) epitaxial material to demonstrate that subsequent photonic devices and systems may be patterned into the integrated material allowing a direct electrical interconnect to embedded CMOS-based electronic systems for new functionalities as electronic-photonic integrated circuitry.
Original language | English (US) |
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Pages (from-to) | D3158-D3166 |
Journal | Journal of the Electrochemical Society |
Volume | 166 |
Issue number | 1 |
DOIs | |
State | Published - 2019 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Renewable Energy, Sustainability and the Environment
- Condensed Matter Physics
- Surfaces, Coatings and Films
- Electrochemistry
- Materials Chemistry