EOS/ESD protection circuit design for deep submicron SOI technology

Sridhar Ramaswamy; Prasun Raha; Elyse Rosenbaum; Sung Mo Kang

doi:10.1109/eosesd.1995.478287

EOS/ESD protection circuit design for deep submicron SOI technology

Sridhar Ramaswamy, Prasun Raha, Elyse Rosenbaum, Sung Mo Kang

Research output: Contribution to journal › Conference article › peer-review

Abstract

Deep submicron silicon-on-insulator (SOI) is potentially an important technology for low voltage applications because of advantages in processing, speed, subthreshold conduction and latchup immunity (Colinge, 1991). However, little attention has been given to EDS/ESD protection circuit design issues for submicron SOI technology. Multi-finger grounded gate NMOS (GGNMOS) devices have been used as effective output protection devices for bulk Si technology. In this paper, the failure modes of GGNMOS devices designed for a 0.3μm fully depleted SOI technology are investigated. A theoretical comparison between the EOS/ESD performance of bulk and SOI technologies is presented. Also, practical design guidelines for effective protection circuit design in SOI technology are provided.

Original language	English (US)
Pages (from-to)	212-217
Number of pages	6
Journal	Electrical Overstress/Electrostatic Discharge Symposium Proceedings
DOIs	https://doi.org/10.1109/eosesd.1995.478287
State	Published - 1995
Event	Proceedings of the 1995 17th Annual Symposium on Electrical Overstress/Electrostatic Discharge - Phoenix, AZ, USA Duration: Sep 12 1995 → Sep 14 1995

ASJC Scopus subject areas

Condensed Matter Physics

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10.1109/eosesd.1995.478287

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title = "EOS/ESD protection circuit design for deep submicron SOI technology",

abstract = "Deep submicron silicon-on-insulator (SOI) is potentially an important technology for low voltage applications because of advantages in processing, speed, subthreshold conduction and latchup immunity (Colinge, 1991). However, little attention has been given to EDS/ESD protection circuit design issues for submicron SOI technology. Multi-finger grounded gate NMOS (GGNMOS) devices have been used as effective output protection devices for bulk Si technology. In this paper, the failure modes of GGNMOS devices designed for a 0.3μm fully depleted SOI technology are investigated. A theoretical comparison between the EOS/ESD performance of bulk and SOI technologies is presented. Also, practical design guidelines for effective protection circuit design in SOI technology are provided.",

author = "Sridhar Ramaswamy and Prasun Raha and Elyse Rosenbaum and Kang, {Sung Mo}",

year = "1995",

doi = "10.1109/eosesd.1995.478287",

language = "English (US)",

pages = "212--217",

journal = "Electrical Overstress/Electrostatic Discharge Symposium Proceedings",

issn = "0739-5159",

publisher = "ESD Association",

note = "Proceedings of the 1995 17th Annual Symposium on Electrical Overstress/Electrostatic Discharge ; Conference date: 12-09-1995 Through 14-09-1995",

}

TY - JOUR

T1 - EOS/ESD protection circuit design for deep submicron SOI technology

AU - Ramaswamy, Sridhar

AU - Raha, Prasun

AU - Rosenbaum, Elyse

AU - Kang, Sung Mo

PY - 1995

Y1 - 1995

N2 - Deep submicron silicon-on-insulator (SOI) is potentially an important technology for low voltage applications because of advantages in processing, speed, subthreshold conduction and latchup immunity (Colinge, 1991). However, little attention has been given to EDS/ESD protection circuit design issues for submicron SOI technology. Multi-finger grounded gate NMOS (GGNMOS) devices have been used as effective output protection devices for bulk Si technology. In this paper, the failure modes of GGNMOS devices designed for a 0.3μm fully depleted SOI technology are investigated. A theoretical comparison between the EOS/ESD performance of bulk and SOI technologies is presented. Also, practical design guidelines for effective protection circuit design in SOI technology are provided.

AB - Deep submicron silicon-on-insulator (SOI) is potentially an important technology for low voltage applications because of advantages in processing, speed, subthreshold conduction and latchup immunity (Colinge, 1991). However, little attention has been given to EDS/ESD protection circuit design issues for submicron SOI technology. Multi-finger grounded gate NMOS (GGNMOS) devices have been used as effective output protection devices for bulk Si technology. In this paper, the failure modes of GGNMOS devices designed for a 0.3μm fully depleted SOI technology are investigated. A theoretical comparison between the EOS/ESD performance of bulk and SOI technologies is presented. Also, practical design guidelines for effective protection circuit design in SOI technology are provided.

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DO - 10.1109/eosesd.1995.478287

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JO - Electrical Overstress/Electrostatic Discharge Symposium Proceedings

JF - Electrical Overstress/Electrostatic Discharge Symposium Proceedings

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Y2 - 12 September 1995 through 14 September 1995

ER -

EOS/ESD protection circuit design for deep submicron SOI technology

Abstract

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