EOS/ESD protection circuit design for deep submicron SOI technology

Sridhar Ramaswamy, Prasun Raha, Elyse Rosenbaum, Sung Mo Kang

Research output: Contribution to journalConference article

Abstract

Deep submicron silicon-on-insulator (SOI) is potentially an important technology for low voltage applications because of advantages in processing, speed, subthreshold conduction and latchup immunity (Colinge, 1991). However, little attention has been given to EDS/ESD protection circuit design issues for submicron SOI technology. Multi-finger grounded gate NMOS (GGNMOS) devices have been used as effective output protection devices for bulk Si technology. In this paper, the failure modes of GGNMOS devices designed for a 0.3μm fully depleted SOI technology are investigated. A theoretical comparison between the EOS/ESD performance of bulk and SOI technologies is presented. Also, practical design guidelines for effective protection circuit design in SOI technology are provided.

Original languageEnglish (US)
Pages (from-to)212-217
Number of pages6
JournalElectrical Overstress/Electrostatic Discharge Symposium Proceedings
StatePublished - Dec 1 1995
EventProceedings of the 1995 17th Annual Symposium on Electrical Overstress/Electrostatic Discharge - Phoenix, AZ, USA
Duration: Sep 12 1995Sep 14 1995

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circuit protection
insulators
silicon
failure modes
immunity
low voltage
conduction
output

ASJC Scopus subject areas

  • Condensed Matter Physics

Cite this

EOS/ESD protection circuit design for deep submicron SOI technology. / Ramaswamy, Sridhar; Raha, Prasun; Rosenbaum, Elyse; Kang, Sung Mo.

In: Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 01.12.1995, p. 212-217.

Research output: Contribution to journalConference article

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