Enhancing the Accuracy of 6T SRAM-Based In-Memory Architecture via Maximum Likelihood Detection

This paper presents a statistical signal processing-based algorithmic approach to enhance the compute signal-to-noise ratio (compute SNR) of 6T SRAM-based analog in-memory computing (IMC) architectures which have recently emerged as an attractive alternative to mainstream digital accelerators for machine learning workloads due to their superior energy efficiency and compute densities. However, today, the compute SNR of analog IMCs is limited by device parameter variations and noise. To overcome this limitation, we propose a maximum likelihood (ML)-based statistical error compensation (MLEC) technique to improve the accuracy of binary dot-products (DPs) realized in 6T (six transistor) SRAM-based analog IMC architectures. The MLEC method involves exploiting the symmetric nature of the 6T SRAM bitcell to extract multiple observations efficiently and employ them for detection purposes. MLEC methods involving two (MLEC-2) and four (MLEC-4) observations are proposed along with efficient architectures to realize them in hardware, e.g., distribution-aware and energy-aware approximations of MLEC-4. Simulations in a commercial bf28 bfnm CMOS process demonstrate that the proposed methods increase the compute SNR for the commonly used 144-dimensional DP by bf5 bfdB-to-bf12 bfdB. This improvement in the bank-level compute SNR leads to a network-level accuracy improvement of up to bf11 % when a ResNet-20 (CIFAR-10 dataset) network is implemented on the IMC. Employing energy models of the IMC, the energy overhead of MLEC is estimated to lie between bf3 %-to-bf10 % resulting in up to bf45.6 % and bf18% increase in energy efficiency (1b-TOPS/W) for a target SNR of bf20 bfdB and ResNet-20 accuracy of bf90 % on the CIFAR-10 dataset, respectively, compared to a conventional (uncompensated) 6T SRAM-based IMC.