Abstract
A fast algorithm for the design of floorplans is described. The algorithm can be used to carry out the complete design of a floorplan or to improve an existing floorplan. It is based on an enhanced bottom-up iterative improvement technique and can obtain good solutions with an increase in speed of approximately two orders of magnitude over an algorithm using the method of simulated annealing.
Original language | English (US) |
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Title of host publication | Unknown Host Publication Title |
Publisher | IEEE |
Pages | 524-527 |
Number of pages | 4 |
ISBN (Print) | 0818608145 |
State | Published - 1987 |
Externally published | Yes |
ASJC Scopus subject areas
- General Engineering