ENHANCED BOTTOM-UP ALGORITHM FOR FLOORPLAN DESIGN.

Thomas R. Mueller, D. F. Wong, C. L. Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A fast algorithm for the design of floorplans is described. The algorithm can be used to carry out the complete design of a floorplan or to improve an existing floorplan. It is based on an enhanced bottom-up iterative improvement technique and can obtain good solutions with an increase in speed of approximately two orders of magnitude over an algorithm using the method of simulated annealing.

Original languageEnglish (US)
Title of host publicationUnknown Host Publication Title
PublisherIEEE
Pages524-527
Number of pages4
ISBN (Print)0818608145
StatePublished - Dec 1 1987
Externally publishedYes

Fingerprint

Simulated annealing

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Mueller, T. R., Wong, D. F., & Liu, C. L. (1987). ENHANCED BOTTOM-UP ALGORITHM FOR FLOORPLAN DESIGN. In Unknown Host Publication Title (pp. 524-527). IEEE.

ENHANCED BOTTOM-UP ALGORITHM FOR FLOORPLAN DESIGN. / Mueller, Thomas R.; Wong, D. F.; Liu, C. L.

Unknown Host Publication Title. IEEE, 1987. p. 524-527.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Mueller, TR, Wong, DF & Liu, CL 1987, ENHANCED BOTTOM-UP ALGORITHM FOR FLOORPLAN DESIGN. in Unknown Host Publication Title. IEEE, pp. 524-527.
Mueller TR, Wong DF, Liu CL. ENHANCED BOTTOM-UP ALGORITHM FOR FLOORPLAN DESIGN. In Unknown Host Publication Title. IEEE. 1987. p. 524-527
Mueller, Thomas R. ; Wong, D. F. ; Liu, C. L. / ENHANCED BOTTOM-UP ALGORITHM FOR FLOORPLAN DESIGN. Unknown Host Publication Title. IEEE, 1987. pp. 524-527
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