Energy optimization in memory address bus structure for application-specific systems

Keyphrases

• Coding Scheme 100%
• Energy Optimization 100%
• Bus Structure 100%
• Memory Address 100%
• Application-specific System 100%
• Energy Consumption 75%
• Capacitance 50%
• Combined Method 50%
• Bus-invert Coding 50%
• Net Reordering 50%
• Ultra-low 25%
• High Repetition Rate 25%
• Coupling Effect 25%
• Energy Dissipation 25%
• High Capacitance 25%
• Simple Circuit 25%
• Statistical Data 25%
• Low Area 25%
• Simulated Annealing Algorithm 25%
• Data Bus 25%
• Efficient Coding 25%
• VLSI Design 25%
• Self-capacitance 25%
• Coupling Capacitance 25%
• Circuit Structure 25%
• Bus Line 25%
• Reordering Techniques 25%
• On-chip Bus 25%
• Fast Simulated Annealing 25%

Computer Science

• Energy Optimization 100%
• Memory Address 100%
• Energy Consumption 75%
• Wire Capacitance 50%
• Experimental Result 25%
• Simulated Annealing 25%
• Statistical Data 25%
• Coupling Capacitance 25%
• Energy Dissipation 25%
• System-on-Chip 25%