Energy-optimal configuration selection for manycore chips with variation

Akhil Langer, Ehsan Totoni, Udatta Palekar, Laxmikant V. Kalé

Research output: Contribution to journalArticlepeer-review


Operating chips at high energy efficiency is one of the major challenges for modern large-scale supercomputers. Low-voltage operation of transistors increases the energy efficiency but leads to frequency and power variation across cores on the same chip. Finding energy-optimal configurations for such chips is a hard problem. In this work, we study how integer linear programming techniques can be used to obtain energy-efficient configurations of chips that have heterogeneous cores. Our proposed methodologies give optimal configurations as compared with competent but sub-optimal heuristics while having negligible timing overhead. The proposed ParSearch method gives up to 13.2% and 7% savings in energy while causing only 2% increase in execution time of two HPC applications: miniMD and Jacobi, respectively. Our results show that integer linear programming can be a very powerful online method to obtain energy-optimal configurations.

Original languageEnglish (US)
Pages (from-to)451-466
Number of pages16
JournalInternational Journal of High Performance Computing Applications
Issue number5
StatePublished - Sep 1 2017


  • energy
  • heterogeneity
  • integer programming
  • low-voltage computing
  • multicore chips
  • near-threshold voltage computing
  • optimization
  • power
  • process variation
  • quadratic integer programming

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture

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