Energy efficient VLSI architecture for linear turbo equalizer

Research output: Contribution to journalArticlepeer-review


In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and decoding in which soft information is iteratively exchanged between the equalizer and decoder. However, turbo equalizers can be computationally complex and hence require significant power consumption. In this paper, we present an energy-efficient VLSI architecture for such linear turbo equalizers. Key architectural techniques include elimination of redundant operations and early termination. Early termination enables powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power. Simulation results show that energy savings in the range 30-60% and 10-60% are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an efficient rescaling method to prevent overflow.

Original languageEnglish (US)
Pages (from-to)49-62
Number of pages14
JournalJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
Issue number1-2 SPEC.ISS.
StatePublished - Jan 2005


  • Architecture
  • Iterative decoder
  • Iterative equalizer
  • Low-power
  • SISO
  • Turbo

ASJC Scopus subject areas

  • Signal Processing
  • Information Systems
  • Electrical and Electronic Engineering


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