Energy-efficient thread-level speculation

Jose Renau; Karin Strauss; Luis Ceze; Wei Liu; Smruti R. Sarangi; James Tuck; Josep Torrellas

doi:10.1109/MM.2006.11

Energy-efficient thread-level speculation

Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas

Research output: Contribution to journal › Article › peer-review

Abstract

Chip multiprocessors with thread-level speculation have become the subject of intense research. This work refutes the claim that such a design is necessarily too energy inefficient. In addition, it proposes out-of-order task spawning to exploit more sources of speculative task-level parallelism.

Original language	English (US)
Pages (from-to)	80-91
Number of pages	12
Journal	IEEE Micro
Volume	26
Issue number	1
DOIs	https://doi.org/10.1109/MM.2006.11
State	Published - Jan 2006

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/MM.2006.11

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@article{82350e2a24464530ad31c56bc2582953,

title = "Energy-efficient thread-level speculation",

abstract = "Chip multiprocessors with thread-level speculation have become the subject of intense research. This work refutes the claim that such a design is necessarily too energy inefficient. In addition, it proposes out-of-order task spawning to exploit more sources of speculative task-level parallelism.",

author = "Jose Renau and Karin Strauss and Luis Ceze and Wei Liu and Sarangi, {Smruti R.} and James Tuck and Josep Torrellas",

year = "2006",

month = jan,

doi = "10.1109/MM.2006.11",

language = "English (US)",

volume = "26",

pages = "80--91",

journal = "IEEE Micro",

issn = "0272-1732",

publisher = "IEEE Computer Society",

number = "1",

}

TY - JOUR

T1 - Energy-efficient thread-level speculation

AU - Renau, Jose

AU - Strauss, Karin

AU - Ceze, Luis

AU - Liu, Wei

AU - Sarangi, Smruti R.

AU - Tuck, James

AU - Torrellas, Josep

PY - 2006/1

Y1 - 2006/1

N2 - Chip multiprocessors with thread-level speculation have become the subject of intense research. This work refutes the claim that such a design is necessarily too energy inefficient. In addition, it proposes out-of-order task spawning to exploit more sources of speculative task-level parallelism.

AB - Chip multiprocessors with thread-level speculation have become the subject of intense research. This work refutes the claim that such a design is necessarily too energy inefficient. In addition, it proposes out-of-order task spawning to exploit more sources of speculative task-level parallelism.

UR - http://www.scopus.com/inward/record.url?scp=33644916639&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33644916639&partnerID=8YFLogxK

U2 - 10.1109/MM.2006.11

DO - 10.1109/MM.2006.11

M3 - Article

AN - SCOPUS:33644916639

SN - 0272-1732

VL - 26

SP - 80

EP - 91

JO - IEEE Micro

JF - IEEE Micro

IS - 1

ER -

Energy-efficient thread-level speculation

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