Energy-efficient thread-level speculation

Jose Renau; Karin Strauss; Luis Ceze; Wei Liu; Smruti R. Sarangi; James Tuck; Josep Torrellas

doi:10.1109/MM.2006.11

Energy-efficient thread-level speculation

Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas

Research output: Contribution to journal › Article › peer-review

Abstract

Chip multiprocessors with thread-level speculation have become the subject of intense research. This work refutes the claim that such a design is necessarily too energy inefficient. In addition, it proposes out-of-order task spawning to exploit more sources of speculative task-level parallelism.

Original language	English (US)
Pages (from-to)	80-91
Number of pages	12
Journal	IEEE Micro
Volume	26
Issue number	1
DOIs	https://doi.org/10.1109/MM.2006.11
State	Published - Jan 2006

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/MM.2006.11

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title = "Energy-efficient thread-level speculation",

abstract = "Chip multiprocessors with thread-level speculation have become the subject of intense research. This work refutes the claim that such a design is necessarily too energy inefficient. In addition, it proposes out-of-order task spawning to exploit more sources of speculative task-level parallelism.",

author = "Jose Renau and Karin Strauss and Luis Ceze and Wei Liu and Sarangi, {Smruti R.} and James Tuck and Josep Torrellas",

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month = jan,

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AU - Renau, Jose

AU - Strauss, Karin

AU - Ceze, Luis

AU - Liu, Wei

AU - Sarangi, Smruti R.

AU - Tuck, James

AU - Torrellas, Josep

PY - 2006/1

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AB - Chip multiprocessors with thread-level speculation have become the subject of intense research. This work refutes the claim that such a design is necessarily too energy inefficient. In addition, it proposes out-of-order task spawning to exploit more sources of speculative task-level parallelism.

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Energy-efficient thread-level speculation

Abstract

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