Energy-efficient performance budgeting in FEC-based high-speed I/O links

Rajan Lakshmi Narasimha, Naresh Shanbhag

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we look at how the introduction of Forward Error Correction (FEC) impacts system design in a high-speed I/O link. We present examples where coding gain maps to improvements in transmit swing, ADC precision, jitter tolerance and comparator offset tolerance.

Original languageEnglish (US)
Title of host publication2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09
Pages41-44
Number of pages4
DOIs
StatePublished - 2009
Externally publishedYes
Event2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09 - Portland, OR, United States
Duration: Oct 19 2009Oct 21 2009

Publication series

Name2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09

Other

Other2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09
Country/TerritoryUnited States
CityPortland, OR
Period10/19/0910/21/09

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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