Energy-efficient leakage-tolerant dynamic circuit technique

Lei Wang, Ram K. Krishnamurthy, K. Soumyanath, Naresh R Shanbhag

Research output: Contribution to journalConference article

Abstract

Technology scaling reduces device threshold voltages to mitigate speed loss due to scaled supply voltages. This, however, exponentially increases leakage power and adversely affects circuit reliability. In this paper, we will investigate the performance degradation in high-leakage digital circuits. It is shown that deep submicron CMOS technologies lead to 60%-70% degradation in noise-immunity due to leakage. Dual-Vt domino designs mitigate the noise-immunity degradation to 30%-40% but inevitably lead to a loss of 20%-30% in circuit speed. To achieve a better noise-immunity vs. performance trade-off, a new dynamic circuit technique - the boosted-source (BS) technique is proposed. Simulation results of wide fan-in gates designed in the Predictive Berkeley BSIM3v3 0.13 μm technology demonstrate 1.6X-3X improvement in noise-immunity at the expense of marginal energy overhead but no loss in delay, as compared with the existing circuit techniques.

Original languageEnglish (US)
Pages (from-to)221-225
Number of pages5
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
StatePublished - Jan 1 2000
EventProceedings of the 13th Annual IEEE International ASIC/SOC Conference - Arlington, VA, USA
Duration: Sep 13 2000Sep 16 2000

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Networks (circuits)
Degradation
Digital circuits
Threshold voltage
Electric potential

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Energy-efficient leakage-tolerant dynamic circuit technique. / Wang, Lei; Krishnamurthy, Ram K.; Soumyanath, K.; Shanbhag, Naresh R.

In: Proceedings of the Annual IEEE International ASIC Conference and Exhibit, 01.01.2000, p. 221-225.

Research output: Contribution to journalConference article

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