Energy-efficient LDPC decoders based on error-resiliency

Eric P. Kim, Naresh R Shanbhag

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Low density parity check (LDPC) codes are used in various communication standards. However, LDPC decoders are complex and power hungry. In this paper, we present an energy-efficient LDPC decoder based on statistical error compensation (SEC). Three different size LDPC codes, (50, 25), (800, 400), and (1800, 900) were implemented with 5 iterations/block. Circuit simulations in a commercial 45 nm process show that the SEC based LDPC decoder can operate at a supply voltage up to 38% less than the nominal voltage and tolerate up to 30× more errors over an SNR range of 3 dB to 8 dB, while maintaining less than 3× degradation in BER. This is equivalent with energy savings of 45.7% compared to conventional LDPC decoders, and 33.2% compared to a sign bit protected LDPC decoder.

Original languageEnglish (US)
Title of host publicationProceedings - 2012 IEEE Workshop on Signal Processing Systems, SiPS 2012
Number of pages6
StatePublished - 2012
Event2012 IEEE Workshop on Signal Processing Systems, SiPS 2012 - Quebec City, QC, Canada
Duration: Oct 17 2012Oct 19 2012

Publication series

NameIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)1520-6130


Other2012 IEEE Workshop on Signal Processing Systems, SiPS 2012
CityQuebec City, QC


  • Error resiliency
  • LDPC
  • Low power

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing
  • Applied Mathematics
  • Hardware and Architecture


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