Energy-efficient hybrid wakeup logic

Michael Huang, Jose Renau, Josep Torrellas

Research output: Contribution to conferencePaper

Abstract

The instruction window is a critical component and a major energy consumer in out-of-order superscalar processors. An important source of energy consumption in the instruction window is the instruction wakeup: a completing instruction broadcasts its result register tag and an associative comparison is performed with all the entries in the window. This paper shows that a very large fraction of the completing instructions have to wake up no more than a single instruction currently in the window. Consequently, we propose to save energy by using indexing to only enable the comparator at the single instruction to wake up. Only in the rare case when more than one instruction needs to wake up, our scheme reverts to enabling all the comparators or a subset of them. For this reason, we call our scheme Hybrid. Overall, our scheme is very effective: for a processor with a 96-entry window, the number of comparisons performed by the average completing instruction with a destination register is reduced to 0.8. The exact magnitude of the energy savings will depend on the specific instruction window implementation. Furthermore, the application suffers no performance penalty.

Original languageEnglish (US)
Pages196-201
Number of pages6
StatePublished - Dec 1 2002
EventProceedings of the 2002 International Symposium on Low Power Electronics and Design - Monterey, CA, United States
Duration: Aug 12 2002Aug 14 2002

Other

OtherProceedings of the 2002 International Symposium on Low Power Electronics and Design
CountryUnited States
CityMonterey, CA
Period8/12/028/14/02

Fingerprint

Energy conservation
Energy utilization

Keywords

  • Issue logic
  • Low power
  • Wakeup logic

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Huang, M., Renau, J., & Torrellas, J. (2002). Energy-efficient hybrid wakeup logic. 196-201. Paper presented at Proceedings of the 2002 International Symposium on Low Power Electronics and Design, Monterey, CA, United States.

Energy-efficient hybrid wakeup logic. / Huang, Michael; Renau, Jose; Torrellas, Josep.

2002. 196-201 Paper presented at Proceedings of the 2002 International Symposium on Low Power Electronics and Design, Monterey, CA, United States.

Research output: Contribution to conferencePaper

Huang, M, Renau, J & Torrellas, J 2002, 'Energy-efficient hybrid wakeup logic' Paper presented at Proceedings of the 2002 International Symposium on Low Power Electronics and Design, Monterey, CA, United States, 8/12/02 - 8/14/02, pp. 196-201.
Huang M, Renau J, Torrellas J. Energy-efficient hybrid wakeup logic. 2002. Paper presented at Proceedings of the 2002 International Symposium on Low Power Electronics and Design, Monterey, CA, United States.
Huang, Michael ; Renau, Jose ; Torrellas, Josep. / Energy-efficient hybrid wakeup logic. Paper presented at Proceedings of the 2002 International Symposium on Low Power Electronics and Design, Monterey, CA, United States.6 p.
@conference{9ecbb5a67c5d4cbb8fb778cad70d234f,
title = "Energy-efficient hybrid wakeup logic",
abstract = "The instruction window is a critical component and a major energy consumer in out-of-order superscalar processors. An important source of energy consumption in the instruction window is the instruction wakeup: a completing instruction broadcasts its result register tag and an associative comparison is performed with all the entries in the window. This paper shows that a very large fraction of the completing instructions have to wake up no more than a single instruction currently in the window. Consequently, we propose to save energy by using indexing to only enable the comparator at the single instruction to wake up. Only in the rare case when more than one instruction needs to wake up, our scheme reverts to enabling all the comparators or a subset of them. For this reason, we call our scheme Hybrid. Overall, our scheme is very effective: for a processor with a 96-entry window, the number of comparisons performed by the average completing instruction with a destination register is reduced to 0.8. The exact magnitude of the energy savings will depend on the specific instruction window implementation. Furthermore, the application suffers no performance penalty.",
keywords = "Issue logic, Low power, Wakeup logic",
author = "Michael Huang and Jose Renau and Josep Torrellas",
year = "2002",
month = "12",
day = "1",
language = "English (US)",
pages = "196--201",
note = "Proceedings of the 2002 International Symposium on Low Power Electronics and Design ; Conference date: 12-08-2002 Through 14-08-2002",

}

TY - CONF

T1 - Energy-efficient hybrid wakeup logic

AU - Huang, Michael

AU - Renau, Jose

AU - Torrellas, Josep

PY - 2002/12/1

Y1 - 2002/12/1

N2 - The instruction window is a critical component and a major energy consumer in out-of-order superscalar processors. An important source of energy consumption in the instruction window is the instruction wakeup: a completing instruction broadcasts its result register tag and an associative comparison is performed with all the entries in the window. This paper shows that a very large fraction of the completing instructions have to wake up no more than a single instruction currently in the window. Consequently, we propose to save energy by using indexing to only enable the comparator at the single instruction to wake up. Only in the rare case when more than one instruction needs to wake up, our scheme reverts to enabling all the comparators or a subset of them. For this reason, we call our scheme Hybrid. Overall, our scheme is very effective: for a processor with a 96-entry window, the number of comparisons performed by the average completing instruction with a destination register is reduced to 0.8. The exact magnitude of the energy savings will depend on the specific instruction window implementation. Furthermore, the application suffers no performance penalty.

AB - The instruction window is a critical component and a major energy consumer in out-of-order superscalar processors. An important source of energy consumption in the instruction window is the instruction wakeup: a completing instruction broadcasts its result register tag and an associative comparison is performed with all the entries in the window. This paper shows that a very large fraction of the completing instructions have to wake up no more than a single instruction currently in the window. Consequently, we propose to save energy by using indexing to only enable the comparator at the single instruction to wake up. Only in the rare case when more than one instruction needs to wake up, our scheme reverts to enabling all the comparators or a subset of them. For this reason, we call our scheme Hybrid. Overall, our scheme is very effective: for a processor with a 96-entry window, the number of comparisons performed by the average completing instruction with a destination register is reduced to 0.8. The exact magnitude of the energy savings will depend on the specific instruction window implementation. Furthermore, the application suffers no performance penalty.

KW - Issue logic

KW - Low power

KW - Wakeup logic

UR - http://www.scopus.com/inward/record.url?scp=0036949790&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036949790&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0036949790

SP - 196

EP - 201

ER -