Energy-efficient hybrid wakeup logic

Michael Huang, Jose Renau, Josep Torrellas

Research output: Contribution to conferencePaperpeer-review


The instruction window is a critical component and a major energy consumer in out-of-order superscalar processors. An important source of energy consumption in the instruction window is the instruction wakeup: a completing instruction broadcasts its result register tag and an associative comparison is performed with all the entries in the window. This paper shows that a very large fraction of the completing instructions have to wake up no more than a single instruction currently in the window. Consequently, we propose to save energy by using indexing to only enable the comparator at the single instruction to wake up. Only in the rare case when more than one instruction needs to wake up, our scheme reverts to enabling all the comparators or a subset of them. For this reason, we call our scheme Hybrid. Overall, our scheme is very effective: for a processor with a 96-entry window, the number of comparisons performed by the average completing instruction with a destination register is reduced to 0.8. The exact magnitude of the energy savings will depend on the specific instruction window implementation. Furthermore, the application suffers no performance penalty.

Original languageEnglish (US)
Number of pages6
StatePublished - 2002
EventProceedings of the 2002 International Symposium on Low Power Electronics and Design - Monterey, CA, United States
Duration: Aug 12 2002Aug 14 2002


OtherProceedings of the 2002 International Symposium on Low Power Electronics and Design
Country/TerritoryUnited States
CityMonterey, CA


  • Issue logic
  • Low power
  • Wakeup logic

ASJC Scopus subject areas

  • Engineering(all)


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