TY - GEN
T1 - Energy-efficient high-speed links using BER-optimal ADCs
AU - Lin, Yingyan
AU - Xu, Aolin
AU - Shanbhag, Naresh
AU - Singer, Andrew
PY - 2011
Y1 - 2011
N2 - We recently explored the concept of using BER-optimal ADCs for high-speed links. In this paper, we study the benefits of BER-optimal ADCs in terms of power savings and relaxation of component specifications in a 90 nm 1.2V CMOS process. These analyses are based on component models for a flash ADC that capture bandwidth limitation of pre-amplifiers and metastability of latches. We show that in the presence of these ADC non-idealities, a 3-bit BER-optimal ADC can provide a 3 dB ADC shaping gain over a 4-bit conventional ADC. The one bit reduction offers power savings of 75% in the VGA and 50% in the ADC. Further, the 3dB ADC shaping gain can be traded-off for a 50% reduction of transmit driver power, a 75% reduction of the pre-amplifier bandwidth, or a saving of one latch stage that leads to a 20% additional power reduction in the ADC.
AB - We recently explored the concept of using BER-optimal ADCs for high-speed links. In this paper, we study the benefits of BER-optimal ADCs in terms of power savings and relaxation of component specifications in a 90 nm 1.2V CMOS process. These analyses are based on component models for a flash ADC that capture bandwidth limitation of pre-amplifiers and metastability of latches. We show that in the presence of these ADC non-idealities, a 3-bit BER-optimal ADC can provide a 3 dB ADC shaping gain over a 4-bit conventional ADC. The one bit reduction offers power savings of 75% in the VGA and 50% in the ADC. Further, the 3dB ADC shaping gain can be traded-off for a 50% reduction of transmit driver power, a 75% reduction of the pre-amplifier bandwidth, or a saving of one latch stage that leads to a 20% additional power reduction in the ADC.
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U2 - 10.1109/EDAPS.2011.6213750
DO - 10.1109/EDAPS.2011.6213750
M3 - Conference contribution
AN - SCOPUS:84864249900
SN - 9781467322881
T3 - 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011
BT - 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011
T2 - 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011
Y2 - 12 December 2011 through 14 December 2011
ER -