Abstract

We recently explored the concept of using BER-optimal ADCs for high-speed links. In this paper, we study the benefits of BER-optimal ADCs in terms of power savings and relaxation of component specifications in a 90 nm 1.2V CMOS process. These analyses are based on component models for a flash ADC that capture bandwidth limitation of pre-amplifiers and metastability of latches. We show that in the presence of these ADC non-idealities, a 3-bit BER-optimal ADC can provide a 3 dB ADC shaping gain over a 4-bit conventional ADC. The one bit reduction offers power savings of 75% in the VGA and 50% in the ADC. Further, the 3dB ADC shaping gain can be traded-off for a 50% reduction of transmit driver power, a 75% reduction of the pre-amplifier bandwidth, or a saving of one latch stage that leads to a 20% additional power reduction in the ADC.

Original languageEnglish (US)
Title of host publication2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011
DOIs
StatePublished - Dec 1 2011
Event2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011 - Hanzhou, China
Duration: Dec 12 2011Dec 14 2011

Publication series

Name2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011

Other

Other2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011
Country/TerritoryChina
CityHanzhou
Period12/12/1112/14/11

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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