This paper describes the impact of crosstalk noise on low power design techniques based on voltage scaling. It is shown that this power saving strategy aggravates the crosstalk noise problem and reduces circuit noise immunity. A new energy-efficient, noise-tolerant dynamic circuit technique is presented to address this problem. In a 0.35 μm CMOS technology and at a given supply voltage, the proposed technique provides an improvement in noise-immunity of 1.8X(for an AND gate) and 2.5X(for an adder carry chain) over domino at the same speed. We use this fact to operate the noise-tolerant circuit at a lower supply voltage to obtain energy savings of about 30%, while expending 30% more area. Also, to achieve a given noise immunity, the proposed technique consumes 40% less energy compared to existing noise-tolerance techniques.
|Original language||English (US)|
|Number of pages||6|
|Journal||Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers|
|State||Published - 1999|
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