Energy-efficient architectures for timing error-tolerant processors

John Sartori, Rakesh Kumar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Architectural design decisions have traditionally been made to maximize processor efficiency during correct operation. However, due to increasing unreliability at the circuit level due to manufacturing and dynamic variations, the cost of maintaining the abstraction of flawless hardware continues to escalate. Recently, error resilience mechanisms have been proposed that allow timing errors during nominal operation and tolerate or correct the errors for an overall reduction in power and/or energy [3]. In this work, we ask whether processors should be architected differently to maximize energy efficiency given the availability of an error resilience mechanism.

Original languageEnglish (US)
Title of host publication2010 International Conference on Energy Aware Computing, ICEAC 2010
DOIs
StatePublished - Dec 1 2010
Event2010 International Conference on Energy Aware Computing, ICEAC 2010 - Cairo, Egypt
Duration: Dec 16 2010Dec 18 2010

Publication series

Name2010 International Conference on Energy Aware Computing, ICEAC 2010

Other

Other2010 International Conference on Energy Aware Computing, ICEAC 2010
Country/TerritoryEgypt
CityCairo
Period12/16/1012/18/10

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Theoretical Computer Science

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