TY - GEN
T1 - Energy-efficient architectures for timing error-tolerant processors
AU - Sartori, John
AU - Kumar, Rakesh
PY - 2010
Y1 - 2010
N2 - Architectural design decisions have traditionally been made to maximize processor efficiency during correct operation. However, due to increasing unreliability at the circuit level due to manufacturing and dynamic variations, the cost of maintaining the abstraction of flawless hardware continues to escalate. Recently, error resilience mechanisms have been proposed that allow timing errors during nominal operation and tolerate or correct the errors for an overall reduction in power and/or energy [3]. In this work, we ask whether processors should be architected differently to maximize energy efficiency given the availability of an error resilience mechanism.
AB - Architectural design decisions have traditionally been made to maximize processor efficiency during correct operation. However, due to increasing unreliability at the circuit level due to manufacturing and dynamic variations, the cost of maintaining the abstraction of flawless hardware continues to escalate. Recently, error resilience mechanisms have been proposed that allow timing errors during nominal operation and tolerate or correct the errors for an overall reduction in power and/or energy [3]. In this work, we ask whether processors should be architected differently to maximize energy efficiency given the availability of an error resilience mechanism.
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U2 - 10.1109/ICEAC.2010.5702294
DO - 10.1109/ICEAC.2010.5702294
M3 - Conference contribution
AN - SCOPUS:79952033087
SN - 9781424482757
T3 - 2010 International Conference on Energy Aware Computing, ICEAC 2010
BT - 2010 International Conference on Energy Aware Computing, ICEAC 2010
T2 - 2010 International Conference on Energy Aware Computing, ICEAC 2010
Y2 - 16 December 2010 through 18 December 2010
ER -