@inproceedings{c6f98560f7594b77bea1e64e2e090eda,
title = "Energy-efficient and metastability-immune timing-error detection and instruction-replay-based recovery circuits for dynamic-variation tolerance",
abstract = "A 65nm resilient-circuit test-chip implements energy-efficient and metastability-immune timing-error detection sequentials with an error-recovery design based on instruction replay to eliminate supply-voltage (VCC) and temperature clock-frequency guardbands as well as to exploit path activation probability for maximizing throughput. Silicon measurements indicate that resilient circuits enable either 25 to 32% throughput gain at equal V cc or 17% Vcc reduction at equal throughput.",
author = "Bowman, {Keith A.} and Tschanz, {James W.} and Kim, {Nam Sung} and Lee, {Janice C.} and Wilkerson, {Chris B.} and Lu, {Shih Lien L.} and Tanay Karnik and De, {Vivek K.}",
year = "2008",
doi = "10.1109/ISSCC.2008.4523227",
language = "English (US)",
isbn = "9781424420100",
series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "402--623",
booktitle = "2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC",
address = "United States",
note = "2008 IEEE International Solid State Circuits Conference, ISSCC ; Conference date: 03-02-2008 Through 07-02-2008",
}