Energy-efficient and metastability-immune timing-error detection and instruction-replay-based recovery circuits for dynamic-variation tolerance

Keith A. Bowman, James W. Tschanz, Nam Sung Kim, Janice C. Lee, Chris B. Wilkerson, Shih Lien L. Lu, Tanay Karnik, Vivek K. De

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A 65nm resilient-circuit test-chip implements energy-efficient and metastability-immune timing-error detection sequentials with an error-recovery design based on instruction replay to eliminate supply-voltage (VCC) and temperature clock-frequency guardbands as well as to exploit path activation probability for maximizing throughput. Silicon measurements indicate that resilient circuits enable either 25 to 32% throughput gain at equal V cc or 17% Vcc reduction at equal throughput.

Original languageEnglish (US)
Title of host publication2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages402-623
Number of pages222
ISBN (Print)9781424420100
DOIs
StatePublished - 2008
Externally publishedYes
Event2008 IEEE International Solid State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: Feb 3 2008Feb 7 2008

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume51
ISSN (Print)0193-6530

Other

Other2008 IEEE International Solid State Circuits Conference, ISSCC
Country/TerritoryUnited States
CitySan Francisco, CA
Period2/3/082/7/08

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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