@inproceedings{4fae6f5b54b646839d9ad92efc3a3b5c,
title = "Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance",
abstract = "Timing-error detection and recovery circuits are implemented in a 65nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous EDS designs while lowering clock energy and removing datapath metastability. Error-recovery circuits replay failing instructions at lower clock frequency to guarantee correct functionality. Relative to conventional circuits, silicon measurements indicate that resilient circuits enable either 25 to 32% throughput gain at equal V CC or at least 17% VCC reduction at equal throughput, resulting in 31 to 37% total power reduction.",
author = "Bowman, {Keith A.} and Tschanz, {James W.} and Kim, {Nam Sung} and Lee, {Janice C.} and Wilkerson, {Chris B.} and Lu, {Shin Lien L.} and Tanay Karnik and De, {Vivek K.}",
year = "2008",
doi = "10.1109/ICICDT.2008.4567268",
language = "English (US)",
isbn = "9781424418114",
series = "Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT",
pages = "155--158",
booktitle = "Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT",
note = "IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2008 ; Conference date: 02-06-2008 Through 04-06-2008",
}