Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance

Keith A. Bowman, James W. Tschanz, Nam Sung Kim, Janice C. Lee, Chris B. Wilkerson, Shin Lien L. Lu, Tanay Karnik, Vivek K. De

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Timing-error detection and recovery circuits are implemented in a 65nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous EDS designs while lowering clock energy and removing datapath metastability. Error-recovery circuits replay failing instructions at lower clock frequency to guarantee correct functionality. Relative to conventional circuits, silicon measurements indicate that resilient circuits enable either 25 to 32% throughput gain at equal V CC or at least 17% VCC reduction at equal throughput, resulting in 31 to 37% total power reduction.

Original languageEnglish (US)
Title of host publicationProceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT
Pages155-158
Number of pages4
DOIs
StatePublished - Sep 22 2008
Externally publishedYes
EventIEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2008 - Minatec Grenoble, France
Duration: Jun 2 2008Jun 4 2008

Publication series

NameProceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT

Other

OtherIEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2008
Country/TerritoryFrance
CityMinatec Grenoble
Period6/2/086/4/08

ASJC Scopus subject areas

  • Human-Computer Interaction
  • Electrical and Electronic Engineering

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