Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance

Keith A. Bowman; James W. Tschanz; Nam Sung Kim; Janice C. Lee; Chris B. Wilkerson; Shin Lien L. Lu; Tanay Karnik; Vivek K. De

doi:10.1109/ICICDT.2008.4567268

Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance

Keith A. Bowman, James W. Tschanz, Nam Sung Kim, Janice C. Lee, Chris B. Wilkerson, Shin Lien L. Lu, Tanay Karnik, Vivek K. De

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Timing-error detection and recovery circuits are implemented in a 65nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (V_CC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous EDS designs while lowering clock energy and removing datapath metastability. Error-recovery circuits replay failing instructions at lower clock frequency to guarantee correct functionality. Relative to conventional circuits, silicon measurements indicate that resilient circuits enable either 25 to 32% throughput gain at equal V _CC or at least 17% V_CC reduction at equal throughput, resulting in 31 to 37% total power reduction.

Original language	English (US)
Title of host publication	Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT
Pages	155-158
Number of pages	4
DOIs	https://doi.org/10.1109/ICICDT.2008.4567268
State	Published - Sep 22 2008
Externally published	Yes
Event	IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2008 - Minatec Grenoble, France Duration: Jun 2 2008 → Jun 4 2008

Publication series

Name	Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT

Other

Other	IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2008
Country/Territory	France
City	Minatec Grenoble
Period	6/2/08 → 6/4/08

ASJC Scopus subject areas

Human-Computer Interaction
Electrical and Electronic Engineering

Access to Document

10.1109/ICICDT.2008.4567268

Cite this

Bowman, K. A., Tschanz, J. W., Kim, N. S., Lee, J. C., Wilkerson, C. B., Lu, S. L. L., Karnik, T., & De, V. K. (2008). Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance. In Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT (pp. 155-158). [4567268] (Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT). https://doi.org/10.1109/ICICDT.2008.4567268

Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance. / Bowman, Keith A.; Tschanz, James W.; Kim, Nam Sung; Lee, Janice C.; Wilkerson, Chris B.; Lu, Shin Lien L.; Karnik, Tanay; De, Vivek K.

Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT. 2008. p. 155-158 4567268 (Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Bowman, KA, Tschanz, JW, Kim, NS, Lee, JC, Wilkerson, CB, Lu, SLL, Karnik, T & De, VK 2008, Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance. in Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT., 4567268, Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT, pp. 155-158, IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2008, Minatec Grenoble, France, 6/2/08. https://doi.org/10.1109/ICICDT.2008.4567268

Bowman KA, Tschanz JW, Kim NS, Lee JC, Wilkerson CB, Lu SLL et al. Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance. In Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT. 2008. p. 155-158. 4567268. (Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT). https://doi.org/10.1109/ICICDT.2008.4567268

Bowman, Keith A. ; Tschanz, James W. ; Kim, Nam Sung ; Lee, Janice C. ; Wilkerson, Chris B. ; Lu, Shin Lien L. ; Karnik, Tanay ; De, Vivek K. / Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance. Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT. 2008. pp. 155-158 (Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT).

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abstract = "Timing-error detection and recovery circuits are implemented in a 65nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous EDS designs while lowering clock energy and removing datapath metastability. Error-recovery circuits replay failing instructions at lower clock frequency to guarantee correct functionality. Relative to conventional circuits, silicon measurements indicate that resilient circuits enable either 25 to 32% throughput gain at equal V CC or at least 17% VCC reduction at equal throughput, resulting in 31 to 37% total power reduction.",

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Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance

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