Energy-efficient and high throughput sparse distributed memory architecture

Mingu Kang, Eric P. Kim, Min Sun Keel, Naresh R Shanbhag

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents an energy-efficient VLSI implementation of Sparse Distributed Memory (SDM). High throughput and energy-efficient Hamming distance-based address decoder (CM-DEC) is proposed by employing compute memory [1], where computation is deeply embedded into a memory (SRAM). Hierarchical binary decision (HBD) is also proposed to enhance area- and energy-efficiency of read operation by minimizing data transfer. The SDM is employed as an auto-associative memory with four read iterations and 16×16 binary noisy input image with input error rates of 15%, 25%, and 30%. The proposed SDM achieves 39× smaller energy delay product with 14.5× and 2.7× reduced delay and energy, respectively as compared to conventional digital implementation of SDM in 45 nm SOI CMOS process with output error rate degradation less than 0.4%.

Original languageEnglish (US)
Title of host publication2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages2505-2508
Number of pages4
ISBN (Electronic)9781479983919
DOIs
StatePublished - Jul 27 2015
EventIEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal
Duration: May 24 2015May 27 2015

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2015-July
ISSN (Print)0271-4310

Other

OtherIEEE International Symposium on Circuits and Systems, ISCAS 2015
CountryPortugal
CityLisbon
Period5/24/155/27/15

Keywords

  • Associative memory
  • Compute memory
  • Machine learning
  • Pattern recognition
  • Sparse Distributed Memory

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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