Energy-efficiency bounds for noise-tolerant dynamic circuits

Research output: Contribution to journalConference article

Abstract

Presented in this paper are lower bounds on energy-efficiency of the mirror noise-tolerant dynamic circuit technique. These lower bounds are derived by solving an energy optimization problem subject to an information-theoretic constraint. Design overheads associated with the noise-tolerant circuit techniques are discussed and incorporated into the optimization problem. Simulation results for a 3-input OR gate transferring information at a rate R = 150 Mbits/sec in 0.35 μm CMOS indicate that the lower bound on energy consumption of the noise-tolerant circuit is 25 f J/bit, which is 31% below that of the conventional domino circuit. This lower bound is achieved when the noise-immunity of the mirror technique is 1.64X more than that of the domino circuit technique.

Original languageEnglish (US)
Pages (from-to)IV-273-IV-276
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume4
StatePublished - Jan 1 2000
EventProceedings of the IEEE 2000 Internaitonal Symposium on Circuits and Systems - Geneva, Switz
Duration: May 28 2000May 31 2000

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Energy efficiency
Networks (circuits)
Mirrors
Energy utilization

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Energy-efficiency bounds for noise-tolerant dynamic circuits. / Shanbhag, Naresh R.; Wang, Lei.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 4, 01.01.2000, p. IV-273-IV-276.

Research output: Contribution to journalConference article

@article{fd9e84533be3475dac72c4d998782160,
title = "Energy-efficiency bounds for noise-tolerant dynamic circuits",
abstract = "Presented in this paper are lower bounds on energy-efficiency of the mirror noise-tolerant dynamic circuit technique. These lower bounds are derived by solving an energy optimization problem subject to an information-theoretic constraint. Design overheads associated with the noise-tolerant circuit techniques are discussed and incorporated into the optimization problem. Simulation results for a 3-input OR gate transferring information at a rate R = 150 Mbits/sec in 0.35 μm CMOS indicate that the lower bound on energy consumption of the noise-tolerant circuit is 25 f J/bit, which is 31{\%} below that of the conventional domino circuit. This lower bound is achieved when the noise-immunity of the mirror technique is 1.64X more than that of the domino circuit technique.",
author = "Shanbhag, {Naresh R.} and Lei Wang",
year = "2000",
month = "1",
day = "1",
language = "English (US)",
volume = "4",
pages = "IV--273--IV--276",
journal = "Proceedings - IEEE International Symposium on Circuits and Systems",
issn = "0271-4310",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Energy-efficiency bounds for noise-tolerant dynamic circuits

AU - Shanbhag, Naresh R.

AU - Wang, Lei

PY - 2000/1/1

Y1 - 2000/1/1

N2 - Presented in this paper are lower bounds on energy-efficiency of the mirror noise-tolerant dynamic circuit technique. These lower bounds are derived by solving an energy optimization problem subject to an information-theoretic constraint. Design overheads associated with the noise-tolerant circuit techniques are discussed and incorporated into the optimization problem. Simulation results for a 3-input OR gate transferring information at a rate R = 150 Mbits/sec in 0.35 μm CMOS indicate that the lower bound on energy consumption of the noise-tolerant circuit is 25 f J/bit, which is 31% below that of the conventional domino circuit. This lower bound is achieved when the noise-immunity of the mirror technique is 1.64X more than that of the domino circuit technique.

AB - Presented in this paper are lower bounds on energy-efficiency of the mirror noise-tolerant dynamic circuit technique. These lower bounds are derived by solving an energy optimization problem subject to an information-theoretic constraint. Design overheads associated with the noise-tolerant circuit techniques are discussed and incorporated into the optimization problem. Simulation results for a 3-input OR gate transferring information at a rate R = 150 Mbits/sec in 0.35 μm CMOS indicate that the lower bound on energy consumption of the noise-tolerant circuit is 25 f J/bit, which is 31% below that of the conventional domino circuit. This lower bound is achieved when the noise-immunity of the mirror technique is 1.64X more than that of the domino circuit technique.

UR - http://www.scopus.com/inward/record.url?scp=0033684153&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033684153&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0033684153

VL - 4

SP - IV-273-IV-276

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

ER -