Energy-efficiency bounds for noise-tolerant dynamic circuits

Research output: Contribution to journalConference articlepeer-review


Presented in this paper are lower bounds on energy-efficiency of the mirror noise-tolerant dynamic circuit technique. These lower bounds are derived by solving an energy optimization problem subject to an information-theoretic constraint. Design overheads associated with the noise-tolerant circuit techniques are discussed and incorporated into the optimization problem. Simulation results for a 3-input OR gate transferring information at a rate R = 150 Mbits/sec in 0.35 μm CMOS indicate that the lower bound on energy consumption of the noise-tolerant circuit is 25 f J/bit, which is 31% below that of the conventional domino circuit. This lower bound is achieved when the noise-immunity of the mirror technique is 1.64X more than that of the domino circuit technique.

Original languageEnglish (US)
Pages (from-to)IV-273-IV-276
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - 2000
EventProceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 - Geneva, Switz, Switzerland
Duration: May 28 2000May 31 2000

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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