Abstract
This paper reports on the performance of four parallel algorithms for simulating an associative cache operating under the LRU (Least-Recently-Used) replacement policy. Three of the algorithms are implemented on the MasPar MP-2. Another algorithm is a parallelization of an efficient serial algorithm on the Intel Paragon. We assess the strengths and weaknesses of these algorithms as a function of problem size and characteristics, and compare their performance on traces derived from execution of three SPEC92 benchmark programs.
| Original language | English (US) |
|---|---|
| Pages | 166-169 |
| Number of pages | 4 |
| DOIs | |
| State | Published - 1995 |
| Externally published | Yes |
| Event | Proceedings of the 9th Workshop on Parallel and Distributed Simulation (PADS'95) - Lake Placid, NY, USA Duration: Jun 14 1995 → Jun 16 1995 |
Other
| Other | Proceedings of the 9th Workshop on Parallel and Distributed Simulation (PADS'95) |
|---|---|
| City | Lake Placid, NY, USA |
| Period | 6/14/95 → 6/16/95 |
ASJC Scopus subject areas
- Engineering(all)