Empirical study of parallel trace-driven LRU cache simulators

David Nicol, Eric Carr

Research output: Contribution to conferencePaperpeer-review

Abstract

This paper reports on the performance of four parallel algorithms for simulating an associative cache operating under the LRU (Least-Recently-Used) replacement policy. Three of the algorithms are implemented on the MasPar MP-2. Another algorithm is a parallelization of an efficient serial algorithm on the Intel Paragon. We assess the strengths and weaknesses of these algorithms as a function of problem size and characteristics, and compare their performance on traces derived from execution of three SPEC92 benchmark programs.

Original languageEnglish (US)
Pages166-169
Number of pages4
DOIs
StatePublished - 1995
Externally publishedYes
EventProceedings of the 9th Workshop on Parallel and Distributed Simulation (PADS'95) - Lake Placid, NY, USA
Duration: Jun 14 1995Jun 16 1995

Other

OtherProceedings of the 9th Workshop on Parallel and Distributed Simulation (PADS'95)
CityLake Placid, NY, USA
Period6/14/956/16/95

ASJC Scopus subject areas

  • General Engineering

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