Algorithmic noise-tolerance (ANT) is an effective statistical error compensation (SEC) technique for designing energy-efficient digital signal processing systems. A conventional ANT system employs an explicit estimator block to compensate for the large magnitude errors in the main block. The estimator presents area and power overheads, as large as 40% of the main block, to the system. In this paper, we propose ARCH-ANT, an architectural level embedded algorithmic noise-tolerance technique. ARCH-ANT achieves the same error compensation functionality as the conventional ANT by embedding the estimator block into the main block. Such embedding eliminates the estimator block and thus improves the system energy efficiency. A general optimization framework is proposed to design ARCH-ANT systems. Simulation results show that when applied to a multiply-accumulate (MAC) unit, 15.9%∼69.4% and 59.2%-72.75% energy savings can be achieved by an 8 ×8 and 16 × 16 ARCH-ANT system, which is 5%∼21.6% more than that of conventional ANT system, with no increase in mean square error (MSE).